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MSPM0G3507: Advanced SPI questions

Rob Oppen
Prodigy 160 points

Part Number: MSPM0G3507
Other Parts Discussed in Thread: SYSCONFIG

Hi,

I have two main questions right now regarding the SPI peripheral in the MSPM0G3507:

1 - Our SPI controller clock rate must be 25MHz and I'd like to run the MSPM0 at the highest CPU clock available given that contstraint. I have it running at 50MHz, which divides the SPI clock down to 25MHz and that's working as expected, but is there really no way to say set the BUSCLK to 75Mhz and divide it down to 25MHz? Or another way to increase MCLK from 50MHz and keep the SPI clock at 25MHz?

2 - I'd like to transfer fragmented blocks of memory out the SPI peripheral without CPU intervention. Does the MSPM0 DMA support linked list transfers to the SPI Tx register? Table mode seems perfect except that it's only capable of doing single transfers not block transfers. If there was a transfer size component, table mode would be perfect. Can I set the DMA into gather mode with different strides? Can I use a second DMA channel to 'feed' the primary DMA channel transfer configurations?

For example, I have a linked list of four data buffers:

Buffer 1 contains 10 bytes of SPI data (starting address 0x2000_1000)

Buffer 2 contains 4 bytes of SPI data (starting address 0x2000_1200)

Buffer 3 contains 512 bytes of SPI data (starting address 0x2000_1240)

Buffer 4 contains 4 bytes of SPI data (starting address 0x2000_2000)

Is the only way to acheive this functionality to do it in the SPI ISR? I have this working, but we're incuring 8uS to setup each transfer (MCLK is set to 50MHz) even with using the DriverLib APIs so in the above example the best case scenario will incur 32uS of transfer setup time.

  • 0
    TI__Genius 13605 points

    Hi Rob,

    #1. If a exact 25MHz SPI frequency is needed, then the only available BUSCLK frequency is 25MHz/50MHz/75MHz. But a 75MHz BUSCLK is not achievable from a 32MHz SYSOSC frequency by SYSPLL. If you do need an exact 25MHz SPI with a higher MCLK frequency than 50MHz,  you could consider use a external crystal such as 20MHz.

    #2 I think the DMA Cascading mode could meet your requirement. You could set the DMA trigger source from another MDA channel done. Please refer to 5.2.5 Initiating DMA Transfers of  MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual (Rev. C) for details.

  • 0 in reply to Pengfei Xie
    Prodigy 160 points

    Hi Pengfei,

    Thank you so much for your reply.

    #1 - Unless I'm missing something, 75MHz is achievable with a 32Mhz SYSOSC using PDIV of 8, QDIV of 75, and CLK0_DIV of 4. However, I don't see a way to divide BUSCLK by 3 to get the desired 25MHz SPI clock while still abiding by the input clock must be 2x SPI clock. The only SPI dividers are CLKDIV (can divide 75Mhz by 3, but will violate the 2x SPI clock) and SCR ((SPI's functional clock frequency)/((SCR+1)*2) so there's no SCR setting that's a divide by 3. I always found this configurability to be really weird and hopefully I'm missing something here.

    #2 - Excellent! Cascading DMA should definitely work for our needs! I appreciate the help.

  • 0 in reply to Rob Oppen
    TI__Genius 13605 points

    Hi Rob,

    #1 Sorry I missed this configuration. In this way, your ULPCLK should be divided to 37.5MHz due to it is limited to be under 40MHz. And as you said, the SPI divider CLKDIV could be set as divided by 3, I'm not sure what does it mean by "it will violate the 2xSPI clock". What weird phenomenon do you meet in this setting?

  • 0 in reply to Pengfei Xie
    Prodigy 160 points

    Hi Pengfei,

    This is according to the sysconfig (v1.25.0) tool:

    Section 25.2.2.4 of the MSPM0 Reference Manual appears to confirm this limitation:
    The SPI includes a programmable bit rate clock divider and prescaler to generate the serial output clock (SCLK). Bit rates supported are up to, the input clocks divided by 2. The input clock selection depends on the specific device, refer to the device data sheet and Clock Control section.

    As a result, there's no way to have a high frequency SPI output clock and a high frequency BUSCLK, which seems like a very odd limitation.

  • +1 in reply to Rob Oppen
    TI__Genius 13605 points

    Hi Rob,

    Oh I see this description. So I think it is a limitation that SPI could not work in 25MHz bit rate with 75MHz CPU clock. Maybe we could just consider to use a 50MHz MCLK. Or use other SPI bit rate such as 20MHz.