Part Number: MSPM0G3519
•MSPM0G3519 have two bank, bank0 and bank1.
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Part Number: MSPM0G3519
Hello Chris,
This behavior is expected from this device, as a power on reset will always cause the MCU to boot from physical Bank0. If you want the image from physical Bank1 to be active immediately after power on, this is something that needs to be configured during boot utilizing the CSC/BCR as described in section 2.2 of that document.
For more information on the CSC, please consult the above document as well as section 4.1 and 4.2 of the TRM.
Best Regards,
Tyler
Dear Morgan,
Thank your for yours reply.
"If you want the image from physical Bank1 to be active immediately after power on, this is something that needs to be configured during boot utilizing the CSC/BCR as described in section 2.2 of that document."
Did you means that the image from physical Bank1 "always" be active immediately after power on ?
My expected behavior is that as a power on reset will always cause the MCU to boot from last execute physical Bank.
Could MSPM0G3519 meet this requirement ?
Physical bank 0 will always be the first as the Boot ROM, BCR, and CSC run from PB0. However, in firmware you can emulate "boot using last executed bank" functionality.
Utilizing CSC, you can have the first piece of executable application code run from the last used bank, which means that while the BSR/CSC will run from PB0, your code will run from the last used physical bank. This requirement is achievable with software, and is not a feature of the MSPM0G3519.
Dear Morgan,
Thank your for your reply.
I fully understood.
Anonner question is that if the MSPM0G3519 run the code in bank1, I can't use J-Link (J-Flash) to erase flash and write flash.
Is this the expected behavior on MSPM0G3519 ?
Hey Chris,
This is expected behavior. In the Dual Bank Flash document, it is mentioned that whichever physical bank is set to main will have read-execute privilege and lose write and erase privileges. So, if you are currently running code in Bank1, you will not be able to write or erase in that bank during execution.
Best Regards,
Tyler
Dear Tyler,
Thank your for your reply.
But when the MCU currently running code in Bank0, I can be able to write or erase in all of the bank include Banl0 by J-Flash V8.34.
when the MCU currently running code in Bank1, I can't be able to write or erase in any of the bank by J-Flash V8.34.
Why ?
Best Regards,
Chris



Hey Chris,
Do you have a launchpad? Are you able to recreate this behavior using the on-board XDS-110 debugger with CCS?
Dear Tyler,
Yes, I have MSPM0G3519 launchpad, but I can't using the on-board XDS-110 debugger with CCS based on “G3519_Bank_Swap_Demo_V3.0.zip” and "MSPM0G3519 Flash Bank Swap Guide V3.0.pptx" from TI FAE.
My CCS didn't have this page, so I used the J-Flash instead of CCS to update FW.
Best Regards,
Chris



Hi Tyler,
Chris develop on Citrix. Since the XDS110 cannot run on Citrix, while the XDS200 can. So they need to use XDS200.
Hello Chris,
Thank you for the patience over the Holiday.
If you are able to use CCS, this is the best way I can match what you are working on. Here are the steps you can take to get your code working on CCS:

Step 1: Please build each project

Step 2: Launch boot in debug mode, do not yet run the debugger though!

Step 3: In view menu, click on the Memory option

Step 4: Memory will open in the bottom window. Click on the down arrow to load memory.

Step 5: Load the programs into each chunk of memory as instructed in the powerpoint
I am actively working to recreate the flash erase issue. If you are able to recreate it with this set-up in CCS, please let me know.