As per the MCF8316C driver requirement, the master IC must introduce an inter-byte delay of 100 µs between each byte for reliable communication during both transmission and reception.
I have implemented the logic and successfully observed the delay between bytes in most cases. However, there is one limitation:
- I am unable to introduce the inter-byte delay between the START condition and the first data byte during reception.
- For all other bytes, the delay works as expected.
Question:
Could you please guide me on how to achieve this requirement in master mode? Specifically:
- Is there any way to insert a delay between the START condition and the first received byte?
- Are there any recommended approaches or hardware features in MSPM0L series that can help implement this?
Additional Details:
- MCU: MSPM0L1228
- Communication: I²C Master Mode
- Requirement: 100 µs inter-byte delay for MCF8316C driver compliance
