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MSPM0G1519: MSPM0G1519 Reset Levels and Peripherals State

Part Number: MSPM0G1519


Hello,

we have a system of 2 MCUs. On is a TI MSPM0G1519 (MCU1) where we implement FWU via standard TI BSL.

To get MCU1 into BSL the other MCU is controlling the NRST and BSL_invoke pins to reset MCU1 and then enter BSL.

When the MCU1 is then executing the BOOTRST the TRM says that SRAM is reset.
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Yet the peripheral state is kept until SYSRST. So my understanding is that if after BOOTRST the BSL is invoked that during the firmware upgrade the previous peripheral state is kept (except for the peripherals needed for FWU e.g. I2C, UART).
 
image.png
 
 Is the above understanding correct? The background is that before entering BSL the application on MCU1 needs to bring the hardware in a safe state by config peripherals accordingly). And that safe hardware state needs to be maintained during FWU via BSL.
  • Hi Macro,

    For MSPM0, both SYSRST and BOOTRST will reset the CPU and peripherals. So the peripheral configurations will be lost if you trigger a ROM primary BSL.

    There are two ways I think you could maintain your peripheral configurations in BSL:

    1. Achieve a secondary BSL, (the system reset will still be triggered), and configure the peripheral at a safe states at the begin of secondary BSL.
    2. Achieve the bootloader within your application program. (The bootloader works as a task or service of application). In this way, you could jump to BSL program without system reset, so your peripheral configurations could be maintained.  
  • Hi Pengrei Xie,

    thx for the answer. Your wrote

    So the peripheral configurations will be lost if you trigger a ROM primary BSL.

    And this is independent how the ROM primary BSL is invoked as SYSRST is mandatory precondition to enter ROM BSL also for software-triggered BSL entry right? 

  • Hi Marco,

    Correct. A SYSRST will be triggered during this BSL invoke process.