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AM2432: I need a manual related to AM243x PCIe EP Register

Kim Wonsik
Prodigy 30 points

Part Number: AM2432
Other Parts Discussed in Thread: TMS320C6674

Hello, I'm currently reviewing the PCIE0_CORE_DBN_CFG_PCIE_CORE register using the spruim2h manual.

However, I discovered that the manual only describes the PCIE0_RC register, not the PCIe Endpoint (EP) register.

To clarify and support the development process, I'm cross-referencing relevant files from MCU SDK v11_00_00_15, including PCIe_v0.h, PCIe_v0.c, and cslr_pcie_ep.h.

While some registers have matching addresses and bit fields, many are not described in the manual or are inconsistent.

Furthermore, the header file lacks bit-level descriptions for several registers, making it difficult to understand accurately.

Could you provide a manual for the PCIe Endpoint (EP) register for the AM2432?

 It would be a great help in correctly configuring the registers and utilizing their functions.

Thank you for your support.

  • 0
    TI__Guru**** 234725 points

    Hello Kim Wonsik, 

    Thank you for the query.

    The serdes0 interface is preconfigured for USB3 or PCIEs.

    We do not recommend customer to configure the SERDES0 registers.

    Is there a specific use case for the registers.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 30 points

    Hello Sreenivasa,

    Thank you for your reply.

    In a previous project, we developed a PCIe Endpoint board using the TMS320C6674, and we are currently applying the AM2432 for our new project.

    On certain PCs with PCIe 3.0 x16 slots, the TMS320C6674-based PCIe EP board successfully links up.

    However, for the AM2432-based PCIe EP board, after calling the Pcie_setSlotClockCnfg and Pcie_cfgEP functions, the Pcie_isLinkUp function returns a timeout.

    Additionally, direct reading of the LtssmState from the Pcie_TiConfDeviceCmdReg register shows PCIE_LTSSM_POLL_COMPLIANCE (3).

    Since the TMS320C6674 allows direct control of the SERDES, BAR, and Debug0 registers, we expect the AM2432 to behave similarly if these registers can be controlled directly.

    Therefore, we request detailed information on the PCIe EP register configuration.

    Regards,
    Wonsik Kim

  • 0 in reply to Kim Wonsik
    TI__Guru**** 234725 points

    Hello Kim Wonsik, 

    Thank you for the inputs.

    Please expect delayed response due to thanksgiving holidays.

    Regards,

    Sreenivasa