Hi,
A stream of characters are sent from a FPGA to one of the UART ports when the controller is started. No characters are received in the Rx buffer. In the flag register (SCIFLR) the bit IDLE is set to '1'. Does that mean that I cant receive characters because the SCI hasn't been synchronized? here is my initialization code for the SCI module:
void
sci1Init(void)
{
/** @b intalise SCI1 @b */
/** - bring SCI out of reset */
sciREG1->GCR0 = 1U;
/** - Disable all interrupts */
sciREG1->CLRINT = 0xFFFFFFFF;
sciREG1->CLRINTLVL = 0xFFFFFFFF;
/** - global control 1 */
sciREG1->GCR1 = (1 << 25)/* enable transmit */
| (1 << 24)/* enable receive */
| (0 << 10)/* Disable multi buffer mode */
| (1 << 5)/* internal clock (device has no clock pin) */
| ((1-1) << 4)/* number of stop bits */
| (1 << 3)/* even parity, otherwise odd */
| (0 << 2)/* no parity */
| (1 << 1);/* asynchronous timing mode */
/** - set baudrate */
sciREG1->BAUD = (3 << 24)/* M */
| (1 << 0);/* Prescaler */
/** - tranmision length */
sciREG1->LENGTH = 7;
/* length */
/** - set SCI pins functional mode */
sciREG1->FUN = (1 << 2)/* tx pin */
| (1 << 1)/* rx pin */
| (0);/* clk pin */
/** - set SCI pins default output value */
sciREG1->DOUT = (0 << 2)/* tx pin */
| (0 << 1)/* rx pin */
| (0);/* clk pin */
/** - set SCI pins output direction */
sciREG1->DIR = (0 << 2)/* tx pin */
| (0 << 1)/* rx pin */
| (0);/* clk pin */
/** - set SCI pins open drain enable */
sciREG1->ODR = (0 << 2)/* tx pin */
| (0 << 1)/* rx pin */
|(0); * clk pin */
/** - set SCI pins pullup/pulldown enable */
sciREG1->PD = (0 << 2)/* tx pin */
|(0 << 1)/* rx pin */
|(0);/* clk pin */
/** - set SCI pins pullup/pulldown select */
sciREG1->PSL = (1 << 2)/* tx pin */
| (1 << 1)/* rx pin */
| (1);/* clk pin */
/** - set interrupt level */
sciREG1->SETINTLVL = (0 << 26)/* Framing error */
| (0 << 25)/* Overrun error */
| (0 << 24)/* Pariry error */
| (0 << 9)/* Receive */
| (0 << 8)/* Transmit */
| (0 << 1)/* Wakeup */
| (0);/* Break detect */
/** - clear interrupt flags */
sciREG1->FLR = 0xFFFFFBFF;
/** - set interrupt enable */
sciREG1->SETINT = (0 << 26)/* Framing error */
| (0 << 25)/* Overrun error */
| (0 << 24) /* Pariry error */
| (0 << 9)/* Receive */
| (0 << 8)/* Transmit */
| (0 << 1)/* Wakeup */
| (0);/* Break detect */
/** - inialise global transfer variables */
g_sciTransfer[0].length = 0;
/** - Finaly start SCI1 */
sciREG1->GCR1 |= (1 << 7);
}
Regards,
Jonas
