I just tried the TF-A K3_SIP_OTP_WRITE and K3_SIP_OTP_READ calls or the TISCI messages TISCI_MSG_WRITE_OTP_MMR/TISCI_MSG_READ_OTP_MMR on an AM62L.
It seems when writing a word is only allowed to be 25bits wide. Writing 0x02000000 results in an error. Writing 0x1 to the next word offset results in the previous word being 0x02000000. So overall it seems there are only 25 fuse bits per 32 bit word, but the encoding from word/bit offset to actual fuse is inconsistent between fuse writing and fuse reading. Is this the intended behaviour? Will it stay like this or is this a bug to be fixed?
Related, https://software-dl.ti.com/tisci/esd/22_01_02/6_topic_user_guides/extended_otp.html refers to the SoC specific documentation:
The extended OTP area can have a maximum of 1024 bits. The extended OTP area is organized into rows of bits. The width of each row can vary based on the device. Please refer to the Chapter 5: SoC Family Specific Documentation for the below details.
Chapter 5 doesn't contain any information about the width of the fuse rows
