Part Number: MSPM0G3507
Hello!
I need to configure DMA by another channels and have some questions to be sure if it is robust approach and approved implementation so we can use it and be sure it is 100% nice.
My bench:
- MSPM0G3507;
- DMA ch0/1/2 are servicing channels for configuration writing;
- DMA ch3 is the channel we configure.
I implemented next pipeline:
- DMA ch0 writes DMAEN=0;
- DMA ch1 writes configuration (I change only DMADA, not sure about other registers);
- DMA ch2 writes DMAEN=1;
- DMA ch3 starts from SW trigger;
Result: new configuration applied and works well.
Main idea here is that configurable DMA channel must be disabled (DMAEN=0) when new configuration is written.
But I don't see such implementation in CCS Examples and documentation, so I have question about a valid and optimal pipeline for it.
Questions:
- Can I find valid pipeline for such implementation?
- Can we write DMAEN=0 in the one transfer with other DMA registers if they are placed in memory after DMAEN, so actually written after?
i.e. DMACTL (with DMAEN bit) is before DMASA, DMADA, DMASZ, so here we actually set DMAEN=0 and only after it write DMASA, DMADA, DMASZ. - Do we need some delay before DMAEN switching for Latching or something?
I checked it already, seems fine, but I need to be sure if it is really correct because documentation is poor for such details.
