Other Parts Discussed in Thread: SK-AM62A-LP, TPS6593-Q1, CSD
Hi, TI engineers.
I would like you help that a phenomenon is occured.
I have been helped in my design several time, and this request is also about the same design.
My design is based on AM62A7 EVM(SK-AM62A-LP, E3).
The MPU is designed with PMIC(TPS6593-q1), LPDDR4(Micron), eMMC(PHISON), ethernet(DP83826ERHBR), etc(CAN, some sensors...).
I have been testing my board for aging to stablize with repetitive warm reset.
It is set to reset every 3~5 min. to test under an extreme condition.
Unfortunately, the reboot stopped after few hours with discontinuance log message.
I had experience kernel panic issue before, but the reason was found out that is core voltage for memory and solved(0.75V -> 0.85V).
However, this case is no log and quite different from previous problem which record log as "kernel panic", I guess.
Do you have any idea what cause is and for the solution?
Should I consider watchdog or can I control PMIC timing sequence?
Regard