• State Resolved
  • Replies 7 replies
  • Subscribers 35 subscribers
  • Views 153 views
  • Users 0 members are here
Support feedback
Options
Options
Related

TMDSCNCD263P: AM263P DCC example fails

Tobias Jäggi
Prodigy 30 points
Part Number: TMDSCNCD263P
Other Parts Discussed in Thread: SYSCONFIG

Running the DCC example of MCU+ SDK for AM263Px fails.

I used

  • AM263Px control card
  • SysConfig 1.25.0
  • MCU+ SDK for AM263Px 11.0.0.19
  • CCS 20.3.1.5__1.9.1

First, I followed SOC Initialization using the Binary Flashed in OSPI memory to setup the EVM.
After flashing sbl_null and switching the EVM boot mode to OSPI, I ran the SDL DCC example on R5FSS0 core 0.
Usecase 3 fails as an unexpected error interrupt is received as seen in the log bellow.

Cortex_R5_0:  DCC Example Test Application
Cortex_R5_0: 
Cortex_R5_0: DCC_Test_init: Init ESM complete 
Cortex_R5_0: 
Cortex_R5_0: USECASE: 0
Cortex_R5_0: Source clock: XTAL_CLK 
Cortex_R5_0: Test clock: RCCLK32K
SDL DCC EXAMPLE TEST: Warning Seed value for valid count exceeds allowed range.
SDL DCC EXAMPLE TEST: Application will run with 0 allowed drift.
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt 
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt 
SDL DCC EXAMPLE TEST: Indicating clock drift/change 
Cortex_R5_0: UC-0 Completed Successfully
Cortex_R5_0: 
Cortex_R5_0: USECASE: 1
Cortex_R5_0: Source clock: XTAL_CLK 
Cortex_R5_0: Test clock: SYSCLK0
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt 
SDL DCC EXAMPLE TEST: No Clock Drift was observed 
Cortex_R5_0: UC-1 Completed Successfully
Cortex_R5_0: 
Cortex_R5_0: USECASE: 2
Cortex_R5_0: Source clock: XTAL_CLK 
Cortex_R5_0: Test clock: SYSCLK0
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and running for some time 
Cortex_R5_0: UC-2 Completed Successfully
Cortex_R5_0: 
Cortex_R5_0: USECASE: 3
Cortex_R5_0: Source clock: RCCLK10M 
Cortex_R5_0: Test clock: SYSCLK0
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Error : DCC Generated error interrupt
SDL DCC EXAMPLE TEST: Error interrupt is not expected 
Cortex_R5_0: UC-3 Failed
Cortex_R5_0: 
Cortex_R5_0:  Few/all tests Failed
  • 0
    Prodigy 30 points

    I had limited success.
    The same DCC example worked on a second AM263Px control card with an identical setup.

    We suspected that the drift of the 10MHz internal clock (RCCLK10M) was the issue since only RCCLK10M related use-cases failed in the DCC example.
    To measure the clock, I created a project which runs a 1ms timer driven by RCCLK10M. In the timer interrupt, a GPIO pin is toggled, which in turn was measured with an oscilloscope.
    The measurements bellow clearly show that RCCLK10M has significant drift (~6% in 1ms) on the board which fails the DCC example.

    Is this behavior within spec or might the board be defective?

    1ms timer driven by RCCLK10M measured on board where DCC example fails


    1ms timer driven by RCCLK10M measured on board where DCC example succeeds

  • 0 in reply to Tobias Jäggi
    TI__Guru 73461 points

    Hi Tobias,

    First of all, apologies for the delayed response!

    Tobias Jäggi said:
    To measure the clock, I created a project which runs a 1ms timer driven by RCCLK10M. In the timer interrupt, a GPIO pin is toggled, which in turn was measured with an oscilloscope.

    I don't think this is ideal way to measure the RCCLK10M, it will not give exact clock frequency of it.

    Instead of this we can route this clock to CLKOUT pin and can do the measurement.

    So, i am suggesting you add below highlighted code into your project.

    Actually, this code helps us to route the RCCLK10M clock to the 72nd pin of the J15A connector.

    Do this to both of your boards and measure the RCCLK10M on your both the boards. Once we got these values, i will check internally acceptable tolerances for internal RC oscillator.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 30 points

    Hi Jagadish,

    Thank you for your reply!
    I did the measurements like you described above:

    RCCLK10M measured on pin 72 on board where DCC example fails - average frequency is 9.39MHz

    RCCLK10M measured on pin 72 on board where DCC example succeeds - average frequency is 9.9MHz

    Interestingly, not only frequency but also amplitude of the two clock signals differ. Both signals were measured with the identical setup, just on differing boards. 

    Looking forward to further inputs from your side. especially the specified tolerance of RCCLK10M.


    Kind regards,

    Tobias

  • 0 in reply to Tobias Jäggi
    TI__Guru 73461 points

    Hi Tobias,

    Actually, for this testing we configured 5% drift and the minimum frequency required from RCCLK10M should be 9.5Mhz. In your case it is 9.39Mhz so that is the reason it is getting failed.

    I require below details from your end:

    1. Are both the cards you are using at your end are of same revisions? Please provide exact PCB number.

    2. Are you using same binary on both the boards, i think yes but please provide a confirmation.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 30 points

    Hi Jagadish

    1. No, both PCBs are not from the same revision.
    PCB# of board where DCC example fail: PROC159A
    PCB# of board where DCC example succeeds: PROC159B

    2. Yes, both boards use the exact same binary.

    Can you please share the specified tolerance of RCCLK10M?

    Thanks

    Tobias

  • 0 in reply to Tobias Jäggi
    TI__Guru 73461 points

    Hi Tobias,

    Tobias Jäggi said:
    PCB# of board where DCC example fail: PROC159A

    I tested with PROC159A board which i had as well, and here also no issue.

    Seems like it is happening for your particular board. I will contact my hardware team once and will get back to you on this.

    --
    Thanks & regards,
    Jagadish.

  • +1 in reply to jagadish gundavarapu
    TI__Intellectual 2380 points

    Hi Tobias and Jagadish,

    This internal RCCLK_10M is only for internal reference and Limp modes, this should not be used for any reference. Also, there is always some variation between Silicon for this internally generate clock.

    The tolerance of this RCCLK_10M is mentioned in the below Section 6.8.8 Safety System in AM263Px Datasheet. Hope this answers the queries you had.

    Thanks,

    Tejas Kulakarni