Other Parts Discussed in Thread: SYSCONFIG
Hello Experts,
I'm using the SPI peripheral in controller (master) mode with SPH = 0, as required by my device, and a frame size of 8 bits.
I've tried filling the TX FIFO with the required frames, either:
by using DMA while SPI is enabled, or
by filling the FIFO first while SPI is disabled, then enabling SPI (to ensure the FIFO never goes empty between frames).
However, in both cases, the CS signal goes inactive briefly between each frame, which breaks the communication with my peripheral.
I’m having a hard time understanding how to avoid this behavior without modifying the SPH setting.
Could you please advise?
More info about my configuration :
SPI clock polarity: I tried both configurations (SP =0 and SPO=1), but I must keep SPH=0 for my peripheral requirement.
Chip Select is hardware-controlled by the SPI module, because in the final application I will need very fast transfers (around 1 µs between SPI bursts), so GPIO-controlled CS is not an option.
SPI is configured entirely using SysConfig, running at 40 MHz SCLK.
TXFIFO fill by DMA :
TXFiFO fill in advance:
Regards,
Manolo Vuarrier
