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CPU behaviour during Error

Lorenz Gruebler
Expert 1075 points

Hello Forum/Engineers,

 

When the ESM issues an error (especially highn severity / error group 3) is there a defined behavior of the MCU?

In my particular application a “fail safe” state is reached when the I/O (CAN, Ethernet, SPI) doesn’t send data any more.

Can this be guaranteed by the ESM Module?

 

Regards,

Lorenz

  • 0
    TI__Mastermind 49120 points

    Hello Lorenz,

    The ESM group3 errors are reserved for severe error conditions as you indicated. These are multi-bit errors for flash or CPU RAM accesses. The ESM response for these errors is only to drive out the nERROR pin low. The assumption is that the CPU cannot be relied upon to function correctly under these conditions.

    The nERROR pin can be monitored by an external supervisor to take further action (reset the micro or keep it permanently under reset by asserting nPORRST). The safety manual for the TMS570LS31x/21x microcontrollers provides more details on the responses to an ESM group3 error event.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Expert 1075 points

    Hello Sunil,

    > "The assumption is that the CPU cannot be relied upon to function correctly under these conditions."

    Thats the point i wanted to know.

    regards, Lorenz