AM263P4: Doubt regarding EPWM base addreses

Hi,

https://dev.ti.com/tirex/explore/content/am26x_academy_10_02_00_03/_build_am26x_academy_10_02_00_03/_images/AM263x_SoC_Interconnect.png

As you can see in the image, to allow access from multiple R5F cores and to avoid latencies due to bus arbiration there are multiple ports to access the epwm regsiters for different cores.

Please refer to TRM section: 3.9

PWM interconnect are divided into 4 groups G0_EPWM, G1_EPWM, G2_EPWM and G3_EPWM accessed using different address regions in the memory map. Any initiator can access an EPWM group while another initiator is accessing a different EPWM group simultaneously. Each interconnect System Interconnect Incorporated has n target ports depending on number of EPWM in the design. After the interconnect, a 4:1 Static Mux can be configured per EPWM using CONTROLSS_GLOBAL_CTRL.EPWM_STATICXBAR_SEL0 & CONTROLSS_GLOBAL_CTRL.EPWM_STATICXBAR_SEL1 register, which statically assigns that EPWM to any of the selection groups – G0 to G3.