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Initialization of Cortex-R4F Registers

Eugene K
Expert 1685 points

Is initialization of Cortex-R4F registers mandatory after each reset or only once in the case of PORST? In other words, do CPU or other resets (including nRST) keep lock-step CPU in 'synchronized' state?

  • 0
    TI__Genius 14205 points

    Hi Eugene,

    Initialization of Cortex-R4F registers are mandatory in case of PORST and reset caused due to STC.
    The reason for the init is when the device powers up / PORST the register contents in two CPUs might have different value, witout init if any of the register is fetched then a CCM error would occur since the CPU's run in lock Step.

    If I remember right there is an app note for this, I will reply to this post with the link.

    Best Regards
    Prathap

  • 0 in reply to Prathap
    Expert 1685 points

    Thank you. Let me ask you follow up question then.

    Does your answer mean that TI guarantees CPU register content (R0-R14, all banked registers and FP D0-D15) staying intact in all other reset cases - EXTRST, SWRST, WDRST, OSCRST and CPURST not caused by STC, assuming that all core voltages are good across those resets? If not then which ones will preserve their content and which ones will not?

    Does your answer also mean that STC test will leave both lock-step cores in 'un-synchronized' state thus requiring the same register initialization as in PORST case?

    Regards,

    Eugene

  • 0 in reply to Eugene K
    TI__Mastermind 23000 points

    Eugene,

    CPU registers should stay the same for all resets excluding nPORRST and STC reset, assuming no faults are present.

    After a STC reset the core registers will always be at the same values but they are not guaranteed to match between the logical CPU and the checker CPU.  This is due to the nature of the auto-generated ATPG test - it does not respect the software programmer's model.  Thus we need to perform a register init after the reset.

    The issue with respect to nPORRST is boot from unpowered state.  If you were to do nPORRST as a warm boot, then in theory all registers would still be synchronized with same contents.

    For the record, the reason this init step is required is that there is a logic cost to ensuring the CPU registers init to the same state in all cases.  ARM made a compromise between logic cost and SW cost - all the control sequence registers have defined reset but the general purpose "data" registers are not initialized by HW.

    Regards,

    Karl