AM263P4-Q1: <ECP> Clarification Regarding CCM Interrupt Handler

Hi Vandana,

As far as I knew, the JTAG needs to be removed to run the CCM related selftest. You can switch to OSPI mode, and load the test code to SPI.

Hi Wang,

I removed the debug cable and flashed my code. Since the while loop checks whether ESM bits 19 and 6 are set and then updates the interrupt_generated_flag inside the interrupt handler, I expected execution to halt at that point when I launch the target configuration. However, the code does not stop there.

Even if the handler is delayed, I would still expect interrupt_generated_flag to be set by the time the interrupt handler executes, but it remains 0, indicating that the interrupt handler is not being entered from the second interrupt (Self test error force).

Hi Vandana,

Are you using the CCM example from the SDK SDL? I tried CCM before, but didn't see this kind of issue.

Hi Wang,

I identified the issue — the VIM ACTIRQ register was not being cleared properly when using the SDK’s ESM High Interrupt Handler. Because of this, only the first interrupt entered the handler. After correcting the VIM clearing, the interrupts are now working as expected. Thank you for your support.

I do need one small clarification though, 

For CCM-related error events such as SDL_ESM0_R5FSS0_COMPARE_ERR_PULSE_0, SDL_ESM0_CCM_0_SELFTEST_ERR, and SDL_ESM0_R5FSS0_VIM_COMPARE_ERR_PULSE_0, Is it mandatory to handle them through interrupts, or is it acceptable to poll the CCM/ESM registers and clear the errors?

Hi Vandana,

The callback function should be responsible to clear the interrupt flags. It is also acceptable to clear the error manually by reading/writing the CCM/ESM status registers directly.

Hi Wang,

Thank you for your inputs, I really appreciate it. I have a question regarding the bitmap structures used in the SDK for CCM. Could you please help me understand these two bitmaps? 

From my understanding, the compare error and bus monitor error events should also be enabled so that the ESM can indicate the error. However, in the current bitmaps, only the self-test error and lockstep compare error event bits are enabled.

Below are the error events I expected to be enabled for R5FSS0 (since I am not using R5FSS1):

• SDL_ESM0_R5FSS0_R5FSS0_BUS_MONITOR_ERR_PULSE_0 (69U)

• SDL_ESM0_R5FSS0_R5FSS0_COMPARE_ERR_PULSE_0 (70U)

• SDL_ESM0_R5FSS0_R5FSS0_VIM_COMPARE_ERR_PULSE_0 (71U)

• SDL_ESM0_R5FSS0_R5FSS0_CPU_MISCOMPARE_PULSE_0 (72U)

• SDL_ESM0_CCM_0_SELFTEST_ERR (83U)

• SDL_ESM0_CCM_0_LOCKSTEP_COMPARE_ERR (84U)

Could you please clarify regarding these error events and why we are using {1,8} for self test error config instead of {2,19} if the self test error event is 83U. 

I'm using SDK version 11.00.00.19. PFA below bit maps for your reference, Thank you. 

  

Ok, I will check, then come back to you later today.