TMS570LS0914: Can't clear DCAN error counters

Part Number: TMS570LS0914
Other Parts Discussed in Thread: HALCOGEN

I'm trying to clear the error counters in the chip, but I'm not having any success.  I've looked through the forums and didn't get much help.

In the error interrupt, I have the following:

    if (notification & (1 << 6)) { /* Too many errors (EWarn) */
        /*
         * Clear the counters by asserting Init, waiting for the ack
         * then deasserting Init.
         */
        node->CTL |= 1;
        while ((node->CTL & 1) != 1)
            ;
        node->CTL &= ~1;
    }

But subsequent interrupts still have the EWarn bit set, and eventually it goes into passive mode (and the counters still don't get reset).  What am I doing wrong?

  • Hi Corey,

    According to the TMS570 Technical Reference Manual, error counters can only be reset automatically at the end of a Bus-Off recovery sequence. The documentation specifically states:

    "Once the Init bit is cleared by the application (or due to the auto-bus-on feature), the device waits for 129 occurrences of Bus Idle (equal to 129 * 11 consecutive recessive bits) before resuming normal operation. The Bus-Off recovery sequence cannot be shortened by setting or resetting the Init bit. At the end of the bus-off recovery sequence, the error counters reset."

    Understanding the Error States

    • Error Warning (EWarn): Triggered when either TEC or REC reaches 96
    • Error Passive: Triggered when either TEC or REC exceeds 127
    • Bus-Off: Triggered when TEC exceeds 255

    What You Should Do Instead

    The error counters will naturally decrease through normal CAN operation:

    1. For successful message transmission: The TEC decreases
    2. For successful message reception: The REC decreases
    3. Fix the root cause: The counters are incrementing because there are actual CAN bus errors occurring (bit errors, stuff errors, ACK errors, etc.)

    Recommended Actions

    1. Investigate the root cause of the CAN errors:

      • Check your CAN bus termination (should be 120Ω at each end)
      • Verify bit timing configuration matches other nodes
      • Check for noise on the CAN bus
      • Ensure proper ground connections
      • Verify CAN transceiver is functioning correctly
    2. Monitor the Error and Status Register to identify what type of errors are occurring

    3. If you reach Bus-Off state, you can recover by:

      • Manually clearing the Init bit to start the recovery sequence
      • Or enabling Auto-Bus-On (ABO) feature in the CAN Control Register
    4. Once errors are fixed, the counters will naturally decrease with successful transmissions/receptions

    --
    Thanks & regards,
    Jagadish.

  • According to the TMS570 Technical Reference Manual, error counters can only be reset automatically at the end of a Bus-Off recovery sequence

    I will point out that is not what the TRM says, it only give that as an option.  But point taken, I understand.

    The error counters will naturally decrease through normal CAN operation

    AFAICT, the TRM never says this.  It would have been helpful information.

    I understand from the CAN architecture that this is really the way things should be.

    I'm causing the errors on purpose, I'm testing out what happens when there are errors.

    The HALCoGen generated interrupt code is calling the CAN error notification on a successful completion of a CAN bus operation because EWarn is set because of excessive errors and it's not calling canMessageNotification().  I was trying to shut that off, but not possible.  So I have to handle canErrorNotification() basically the same as canMessageNotification().  Except that the HALCoGen generated code is that it masks off bits I need when calling canErrorNotification() to know if it actually completed.  I had to add my own user code there to work around this.

    The TRM give no helpful guidance on how to handle error situations.

    But I know what to do now.