Part Number: MSPM0G3519
Other Parts Discussed in Thread: SYSCONFIG
Hi champs,
I am asking this for our customer.
SDK: mspm0_sdk_2_07_00_05
CCS: 20.3.1.5
When the user uses Sysconfig and chooses "Bit Error Corrected interrupt" below, there will be generated codes below, which causes code building errors.
Do you see this on your side?
If yes, how do you solve it?
Code generated...
Hi Wayne,
Referring to MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual (Rev. C), the Bit Error Corrected interrupt is not defined in MCAN_IR register, so it could not be handled in MCAN line 0 and line 1 interrupt.
Instead, there is a standalone interrupt for Bit Error Corrected interrupt, please see below for sysconfig setting and interrupt handler.
Hi Pengfei,
We are confused.
There are two kinds of bit error below
1) single error correction (correctable)
2) Double bit error (uncorrectable)
And
"Bit Error Corrected interrupt = DL_MCAN_IIDX_SINGLE_ERROR_CORRECTION"
That is, BECE below?
Is it right?
Hi Wayne,
Yes, the DL_MCAN_IIDX_SINGLE_ERROR_CORRECTION is the single error correction (correctable), and DL_MCAN_IIDX_DOUBLE_ERROR_DETECTION is Double bit error (uncorrectable).
These two SRAM error interrupts are parallel with MCAN line 1 and line 2 interrupts, so they need to be configured as I show in last reply.
Best Regards,
Pengfei
