AM2431: About tWPRE in LPDDR4

Hi,

I’ve assigned your query to the concerned expert. Please note that responses may be delayed due to the Christmas and New Year holidays. Please feel free to ping this thread if you don't receive a response latest by Jan 1st week

Regards,
Johnson

Hi Johnson,

Thank you for assigning my query to the concerned expert and for letting me know about the possible delay due to the holidays.

I appreciate your support and will follow up if needed.

Best regards,

Futoshi

Hello Futoshi,

Thank you for the note and understanding.

Regards,

Sreenivasa

Can you post the DDR configuration file you are using for this test (in u-boot under arch/arm/dts)?  Did you use the DDR register configuration tool to generate a DDR configuration file for your board?   You may be using an old configuration file which does not enable the WDQS extension for write preamble.

Regards,

James

Hi James,

There is no folder named arch/arm/dts in u-boot.

By “DDR register configuration tool,” do you mean sysconfig?

I have attached the header file generated by sysconfig.

6281.cpu_ti_board_ddrReginit.h

Sorry, i didn't realize you were using AM24x.  For MCU+ SDK, the file is located in source/drivers/ddr/v0/soc/am64x_am243x

The file you posted is old (generated with v0.08.80 of the tool), so it would not have the WDQS extension enabled that i mentioned.  You would need to generate a new file with the latest Sysconfig tool: https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM243x_ALV_beta

build the code, and check the write preamble again.

Regards,

James

Hi James,

We have identified an issue with “write preamble” in products that have already been shipped.

These products operate LPDDR4 at 533?MHz.

However, the latest SysConfig tool does not allow configuration for 533?MHz.

Could you please advise on a method to ensure the correct timing for “write preamble” when operating at 533?MHz, such as directly modifying the header file or any other approach?

You can enable the WDQS feature with the following changes:

#define DDRSS_PHY_65_DATA 0x00000104

#define DDRSS_PHY_321_DATA 0x00000104

Regards,

James

Hi James,

Regards,

Futoshi

Hi James,

I haven’t tried the method you taught me yet.

The timing of tWPRE might not have been an issue? - it could just be that I was interpreting the waveform incorrectly.

By the way, is the method you shared intended to support WDQS extension?

If so, then the older sysconfig might simply not support WDQS extension, rather than having a problem with tWPRE timing.

Is that correct?

Regards,

Futoshi

Can you explain more on your mis-interpretation?  

futoshi kawarazaki said:

By the way, is the method you shared intended to support WDQS extension?

Yes, the changes provided will enable the WDQS extension feature.  This is enabled by default if you use the latest configuration tool, but i provided the specific register for the feature so you can test it with the older configuration.

futoshi kawarazaki said:

If so, then the older sysconfig might simply not support WDQS extension, rather than having a problem with tWPRE timing.

Is that correct?

The older config simply had the WDQS extension feature disabled.  I think the tWPRE timing should be correct in the older config as well.    My understanding is that some memories need an extended write preamble beyond what JEDEC spec states.

Regards,

James

Hi James,

I have requested a waveform evaluation from the memory vendor.

The memory vendor informed me that the tWPRE is only 0.5 tCK.

Therefore, I inquired about how to adjust the tWPRE.

I examined the waveform on a different board from the one I requested the memory vendor to evaluate.

As a result, the tWPRE appeared to have no issues.

Although the DQ transitions between H and L earlier, I believe that the DQ at that timing is not being used.

I am currently asking the memory vendor whether my understanding is correct.

Regards,

Futoshi