AM2431: For MCSPI peripheral with DMA, how to transfer more than 4096 bytes

Hello,

I am not sure on which SDK version you are testing the application on. I would recommend using the latest one. Here it is: https://www.ti.com/tool/download/MCU-PLUS-SDK-AM243X/11.02.00.24

The reason being I found few commits which might help resolve your issue with DMA.

Here you go:

1. https://github.com/TexasInstruments/mcupsdk-core/commit/4d768588852b0bc90a30a45b6355260c443eff05#diff-57541bc9ca53109e199e08e3071a8375f7a64f5f256605dd7b84c8388baacd21

2. https://github.com/TexasInstruments/mcupsdk-core/commit/1c562a26b166792e3e7f1ac5bb4b4a19430aeab7

There are other changes as well with are aimed towards improving the MCSPI driver as a whole.

Also recommended to read this GUIDE, if you have not already: e2e.ti.com/.../faq-sk-am64b-mcspi-integration-guide

Regards,

Vaibhav

Yes, it fixed the issue. Initially, we could only transfer a maximum of 2048 bytes of data per DMA channel, so we considered referencing the NETWORK module's approach of linking multiple DMA channels. However, it was later discovered that this was unnecessary. Currently, we use a single DMA channel and have achieved the required functionality.

Hi Vaibhav,

We directly modified the application code. The original code contained numerous intermediate debugging sections that have not yet been organized, so I extracted the key code. Please kindly help review whether there are any issues with our implementation.

The key strategy is as follows:
We added an SPI CS rising edge interrupt. After starting the DMA transmit/receive, if we receive a CS interrupt instead of an SPI completion interrupt, we reset the DMA and retrieve the length of the data already received through the following function deInitMcspiSlaveDMACh().

extern MCSPI_ChConfig       *gConfigMcspiChCfg[];
int32_t myUdmaDeInitCh(Udma_ChHandle chHandle,
                                  uint32_t  isChEnabled);
								  
								 

void terminateMcspiSlaveDMA()
{
    int32_t                retVal;
    uint32_t index = 2;
    uint32_t chCnt = 0;
    uint64_t               pDesc;
    MCSPILLD_Handle        hMcspi;
    MCSPILLD_InitHandle    hMcspiInit;
    MCSPI_Config *config = NULL;
    MCSPI_Object *obj    = NULL;
    uint32_t               chNum, effByteCnt, peerData;
    MCSPI_UdmaChConfig    *dmaChConfig;
    MCSPI_Transaction     *transaction;
    CSL_UdmapCppi5HMPD    *pHpd;
    MCSPI_ChObject        *chObj;
    uint32_t               baseAddr, irqStatus = 0U;
    Udma_ChHandle          rxChHandle, txChHandle;
    int32_t                status = MCSPI_STATUS_SUCCESS;
    uint8_t *pRxHpdMem, *pTxHpdMem;
    MCSPI_ChConfig      *chConfig;

    config = &gMcspiConfig[index];
    obj = config->object;
    hMcspi = obj->mcspiLldHandle;
    hMcspiInit   = hMcspi->hMcspiInit;
    baseAddr     = hMcspi->baseAddr;
    transaction  = &hMcspi->transaction;
    chNum        = transaction->channel;
    chObj        = &hMcspi->hMcspiInit->chObj[chNum];
    dmaChConfig  = (MCSPI_UdmaChConfig *)chObj->dmaChCfg;
    rxChHandle   = dmaChConfig->rxChHandle;
    txChHandle   = dmaChConfig->txChHandle;
    effByteCnt   = transaction->count << chObj->bufWidthShift;
    pRxHpdMem    = dmaChConfig->rxHpdMem;
    pTxHpdMem    = dmaChConfig->txHpdMem;
    chConfig    = gConfigMcspiChCfg[index];

    hMcspi->transaction.count = 0;


	pHpd = (CSL_UdmapCppi5HMPD *)((uint8_t *) pTxHpdMem + i * sizeof(CSL_UdmapCppi5HMPD));
	CacheP_inv(pHpd, dmaChConfig->hpdMemSize, CacheP_TYPE_ALLD);

	pHpd = (CSL_UdmapCppi5HMPD *)((uint8_t *) pRxHpdMem + i * sizeof(CSL_UdmapCppi5HMPD));
	CacheP_inv(pHpd, dmaChConfig->hpdMemSize, CacheP_TYPE_ALLD);

	retVal = Udma_ringDequeueRaw(Udma_chGetCqRingHandle(txChHandle), &pDesc);
	if (retVal < 0)
		retVal = Udma_ringFlushRaw(Udma_chGetFqRingHandle(txChHandle), &pDesc);

	retVal = Udma_ringDequeueRaw(Udma_chGetCqRingHandle(rxChHandle), &pDesc);
	if (retVal < 0)
		retVal = Udma_ringFlushRaw(Udma_chGetFqRingHandle(rxChHandle), &pDesc);
	else
	{
		pHpd   = (CSL_UdmapCppi5HMPD *)(uintptr_t)pDesc;
		if (retVal == UDMA_SOK)
		{
			status = MCSPI_TRANSFER_COMPLETED;
		}
		else
		{
			status = MCSPI_TRANSFER_FAILED;
			//hMcspi->hMcspiInit->errorCallbackFxn(hMcspi, status);
		}

		if ((status == MCSPI_TRANSFER_COMPLETED) &&
			(MCSPI_TR_MODE_TX_ONLY != chObj->chCfg->trMode))
		{
			if(dmaChConfig->isCqRingMem != UDMA_COMP_QUEUE_RING_MEM_ENABLED){
				retVal = Udma_getPeerData(rxChHandle, &peerData);
				DebugP_assert(retVal == UDMA_SOK);
	//            startTicks = hMcspiInit->clockP_get();
	//                    while ((effByteCnt != peerData) && (elapsedTicks < transaction->timeout))
	//                    {
	//                        retVal += Udma_getPeerData(rxChHandle, &peerData);
	//                        elapsedTicks = hMcspiInit->clockP_get() - startTicks;
	//                    };
				/* Clear Data */
				retVal += Udma_clearPeerData(rxChHandle, peerData);
			}
			DebugP_assert(retVal == UDMA_SOK);


			/* Get Byte count received */
			effByteCnt = (pHpd->descInfo & CSL_UDMAP_CPPI5_PD_DESCINFO_PKTLEN_MASK) >> CSL_UDMAP_CPPI5_PD_DESCINFO_PKTLEN_SHIFT;
			hMcspi->transaction.count += (effByteCnt >> chObj->bufWidthShift);
		}
	}


    /* Stop MCSPI Channel */
    MCSPI_lld_dmaStop(hMcspi, chObj, chNum);
    hMcspi->state = MCSPI_STATE_READY;

    irqStatus = CSL_REG32_RD(baseAddr + CSL_MCSPI_IRQSTATUS);
    if ((irqStatus & ((uint32_t)CSL_MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK)) != 0U)
    {
      retVal = MCSPI_TRANSFER_CANCELLED;
      hMcspi->errorFlag |= MCSPI_ERROR_RX_OVERFLOW;
    }

    if (((irqStatus & ((uint32_t)CSL_MCSPI_IRQSTATUS_TX0_UNDERFLOW_MASK << (4U * chNum))) != 0U) &&
      ((hMcspiInit->msMode == MCSPI_MS_MODE_PERIPHERAL)))
    {
      retVal = MCSPI_TRANSFER_CANCELLED;
      hMcspi->errorFlag |= MCSPI_ERROR_TX_UNDERFLOW;
    }

    if(hMcspi->errorFlag != 0U)
    {
      hMcspi->hMcspiInit->errorCallbackFxn(hMcspi, retVal);
    }
    else
    {
      hMcspi->hMcspiInit->transferCallbackFxn(hMcspi, MCSPI_TRANSFER_COMPLETED);
    }

}


//disable DMA Channel
int32_t myUdmaDeInitCh(Udma_ChHandle chHandle,
                                  uint32_t  isChEnabled)
{
    int32_t udmaStatus = UDMA_SOK;
    int32_t status = MCSPI_STATUS_SUCCESS;

    if(isChEnabled == MCSPI_UDMA_CHANNEL_ENABLE)
    {
        /* Disable Channel */
        udmaStatus = Udma_chDisable(chHandle, UDMA_DEFAULT_CH_DISABLE_TIMEOUT);
        DebugP_assert(UDMA_SOK == udmaStatus);
    }

    if(udmaStatus == UDMA_SOK)
    {
        status = MCSPI_STATUS_SUCCESS;
    }
    else
    {
        status = MCSPI_STATUS_FAILURE;
    }


    return status;
}

//disable DMA Channel TX
int32_t myUdmaDeInitChTX(Udma_ChHandle chHandle,
                                  uint32_t  isChEnabled)
{
    Udma_DrvHandleInt   drvHandle;
    CSL_PktdmaRT        pktdmaRtStatus;
    Udma_ChHandleInt    chHandleInt = (Udma_ChHandleInt) chHandle;

    drvHandle = chHandleInt->drvHandle;

    /*
     *  TRT_CTL Bit31 TX_ENABLE
     *  This field enables or disables the channel. Disabling a channel
        halts operation on the channel after the current block transfer is
        completed. Disabling a channel in the middle of a packet transfer
        may result in underflow conditions in the attached application block
        and data loss. When a channel is disabled, the implementation may
        choose to reset all state for the channel. The pause bit should
        be asserted instead of clearing enable directly if the intent is to
        temporarily pause the channel. This field is encoded as follows: 0 =
        channel is disabled 1 = channel is enabled This field will be cleared
        by HW after a teardown is requested to indicate that the channel
        teardown is complete.
     * */
    pktdmaRtStatus.enable   = FALSE;
    pktdmaRtStatus.teardown = FALSE;
    pktdmaRtStatus.forcedTeardown = FALSE;

    (void) CSL_pktdmaSetTxRT(&drvHandle->pktdmaRegs, chHandleInt->txChNum, &pktdmaRtStatus);

    return UDMA_SOK;
}

int32_t deInitMcspiSlaveDMACh()
{
    int32_t              status = SystemP_SUCCESS;
    uint32_t index = 2;
    MCSPI_ChConfig      *chConfig;
    MCSPI_Config        *config = NULL;
    MCSPI_Object        *obj    = NULL;
    MCSPILLD_Handle      mcspiLldHandle;
    uint32_t chCnt = 0;
    MCSPI_ChObject      *chObj;
    MCSPI_UdmaChConfig  *dmaChConfig;

    config = &gMcspiConfig[index];
    obj = config->object;
    mcspiLldHandle                = obj->mcspiLldHandle;

    chConfig    = gConfigMcspiChCfg[index];

    chObj            = &mcspiLldHandle->hMcspiInit->chObj[chCnt];
    dmaChConfig      = (MCSPI_UdmaChConfig *)chObj->dmaChCfg;

    myUdmaDeInitCh(dmaChConfig->rxChHandle, dmaChConfig->isChEnabled);

    myUdmaDeInitChTX(dmaChConfig->txChHandle, dmaChConfig->isChEnabled);

    terminateMcspiSlaveDMA();

    return status;
}

Hi Vaibhav,

As show below, MCSPI is configured in polling mode in SYSCFG, and then the following function is actively called in the main function to initialize the DMA.