TMS570LS3137: Hardware development guide

Hi Vivek,

vivek khare said:

System-Level Documentation

• Is there a System Design Guide, Hardware Design Guide, or reference schematic/PCB available specifically for the TMS570LS31xx family?

• Any TI reference designs or application notes that you would recommend?

TMS570LS31 Hercules Development Kit (TMDS570LS31HDK):

TMDS570LS31HDK Development kit | TI.com

You can find its schematic and design files here:

Here are some links that you may find helpful:

https://software-dl.ti.com/hercules/hercules_docs/latest/hercules/index.html

https://www.ti.com/reference-designs/index.html

https://www.pcbway.com/blog/2/PCB_Layout_Guidelines_and_Tips.html

vivek khare said:

Power Supply & Capacitor Selection

Decoupling Capacitor Recommendations:

• Core, I/O, and Analog Supply Decoupling: TI recommends connecting a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling capacitor to the DVCC and DVSS pins(3)
• Capacitor Types:
  • Use X7R or better ceramic capacitors for stable dielectric characteristics over temperature
  • For bulk capacitance, a hybrid network combining ceramic bypass capacitors with tantalum bulk capacitors is recommended
  • Polymer or tantalum capacitors along with 0.1µF and 1µF ceramic capacitors work well as bypass capacitors

Placement Guidelines:

• Place decoupling capacitors as close as possible to the power pins
• Do not place output capacitors more than 10 mm away from the regulator
• Use short, wide traces to minimize inductance

vivek khare said:

Clock Configuration

Oscillator/Crystal Specifications:

• The TMS570LS3137 main oscillator circuit connects to an external crystal through pins X1 and X2 (or OSCIN/OSCOUT)
• If a resonator is used, its ground terminal should be connected to the pin VSSOSC (not board ground)
• Crystal frequency range: Typically 10-20 MHz for Hercules devices
• Choose load capacitors (C4 and C6) carefully according to crystal specification

PCB Layout Precautions:

• Place all crystal circuit components as close as possible to the respective device pins
• Route the crystal circuit traces on the outer layer of the PCB and minimize trace lengths to reduce parasitic capacitance
• Minimize crosstalk from other signals - keep any other nearby traces double-spaced away
• Spacing should be kept minimal between crystal traces, with electromagnetic fields canceling each other out

vivek khare said:

Pin Functions & Configuration

• Best practices for handling:

  • Boot configuration pins

  • Test / JTAG pins

  • Unused pins (pull-ups, pull-downs, or leave floating)

• Any common mistakes to avoid during schematic capture

JTAG/Test Pins:

(+) TMS570LC4357-SEP: Programming TMS570LC4357-SEP with LP-XDS110 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

(+) TMS570LS1227: nTRST pin for TMS570LS1227 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

• The JTAG port has dedicated pins: TMS, TDI, TDO, and TCK (Note: TMS570 devices typically don't have a TRST pin)
• TMS pin: Should have an external 2.2 kΩ pull-up resistor to VDDIO to keep JTAG in reset during normal operation
• The TMS570 also supports cJTAG (IEEE 1149.7), a compact 2-pin JTAG interface using only TMS and TCK

Reset Pins:

• nPORRST: When active, the ERROR pin is in high impedance state
• External circuitry required: Either a pull-up resistor to VDD or a reset control circuit must actively pull NRST high for the device to start
• There is no internal pull-up resistor on NRST

Unused Pins:

• For GPIO pins, pull-up/pull-down control is available through registers
• Internal pull-up and pull-down resistors on input pins ensure outputs are held in known states when pins are floating
• Best practice: Check the datasheet for default internal pull configurations on specific pins

vivek khare said:

PCB Layout Guidelines

• Minimum of four layers is required to accomplish a low EMI PCB design
• Layer stacking order (top-to-bottom):
  1. High-speed signal layer
  2. Ground plane
  3. Power plane
  4. Low-frequency signal layer

Grounding and Power Plane Considerations:

• Use ground planes instead of ground traces where possible to lower current-path inductance
• Use multipoint and thicker grounds where you want ESD currents to flow
• A mostly continuous ground plane on the bottom layer allows for VCC reverse current to follow the forward path, minimizing overall current loop
• Use multiple vias to connect power planes to internal layers

EMI/ESD Robustness:

• Minimize the total area of switching nodes to help reduce radiated EMI
• Follow TI's application notes on PCB layout for reduced EMI

--
Thanks & Regards,
Jagadish.