Part Number: AM263P4-Q1
Other Parts Discussed in Thread: CSD
After sending the command to the emmc to read the CSD register, I am waiting for the CC bit of the MMC_STAT register to be set to read the responses received on the response registers(MMC_RSP10, MMC_RSP32
MMC_RSP54, MMC_RSP76). According to the description of the field CC bit, the Command complete IRQ is set after the responses are received. But I am not able to see the responses after waiting for the CC bit to be set. The response registers are updated after waiting for more than 300 microseconds after CC is set for 400KHZ clk.
Is this delay expected ? Also could you please let us know what is the delay we need to provide to read the response and data for the commands based on the different clock frequency? I need to set a timeout for checking CC and TC to set as true. Can you please provide the delay expected for these bits to set different clock frequency?
