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MSPM0L1305: Need clarification on using internal OPA

Preetham Y
Prodigy 10 points
Part Number: MSPM0L1305


Hi, 

We are using the MSPM0L1305SRTRR in our design, with an estimated annual volume of around 100K units.

I plan to use the internal OPA in buffer mode, with its output routed to the ADC. My understanding is that connecting the input signal to PA18/A7 (pin 14) and configuring this pin as the non-inverting input should be sufficient for the hardware. The rest—such as tying the OPA’s output to its inverting input and routing the OPA output to the ADC—can be handled internally by selecting the appropriate MUX settings. Is this correct? Externally only one pin is enough right?

Additionally, I am using PA0 and PA1 for bootloading via I²C. After bootloading, can these pins be reused as a normal I²C interface supporting Fast-mode Plus (Fm+)?

Please confirm if my understanding is correct or if there are any additional considerations.

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  • 0
    TI__Genius 11181 points

    Hi,

    Preetham Y said:
    I plan to use the internal OPA in buffer mode, with its output routed to the ADC. My understanding is that connecting the input signal to PA18/A7 (pin 14) and configuring this pin as the non-inverting input should be sufficient for the hardware. The rest—such as tying the OPA’s output to its inverting input and routing the OPA output to the ADC—can be handled internally by selecting the appropriate MUX settings. Is this correct? Externally only one pin is enough right?

    Yes, your understanding is correct.

    Preetham Y said:
    Additionally, I am using PA0 and PA1 for bootloading via I²C. After bootloading, can these pins be reused as a normal I²C interface supporting Fast-mode Plus (Fm+)?

    Yes, you can.

    Regards,

    Zoey

  • 0 in reply to Zoey Wei
    Prodigy 10 points

    Hi Zoey,

    Thanks for the reply..

    We have selected the MSPM0L1305SRTRR package, which has 16 pins. The NRST pin is multiplexed with several functions, including BSL_I2C_SCL. In our design, we need to use this pin as BSL_I2C_SCL and therefore plan to use a 1 kΩ pull-up resistor for I²C compliance. Although TI recommends a 47 kΩ pull-up for NRST, using a 1 kΩ pull-up should not cause any issue because it still ensures the pin is held high to VDD for proper device startup and meets I²C timing requirements. Is my understanding correct?