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AM2612: About RGMII topic

Lu Bruce
Prodigy 20 points
Part Number: AM2612


Hi TI support team,

Regarding the CPSW module, I have a solution to help confirm whether it is supported : 

(1) Can the CPSW module receive messages from RGMII2 and send them directly through RGMII1? 

(2) If the first item is supported, how to configure the CPSW module? 

 

The network communication architecture is shown in the following figure, Please help confirm whether it is supported on the AM2612 chip.

QrohbOPgGouUWyxmW6Cc6fJenth.jpg

 

Best regards,
Bruvin Lu. 

  • 0
    TI__Expert 4285 points

    Hi Bruvin Lu,

    Lu Bruce said:
    Can the CPSW module receive messages from RGMII2 and send them directly through RGMII1? 

    Does this mean all kinds of ethernet packets or certain packets, for example multicast packets or broadcast packets and so on ?

    Regards,

    Aswin

  • 0
    Prodigy 20 points

    Hi Aswin Sankar,

    What I mean is whether the Ethernet data of PORT2 (including all packets from FPGA ) can be directly forwarded to PORT1 for transmission to PHY, and the data input by PORT1 does not need to be forwarded to PORT2 but uploaded to the Eth driver.

  • 0 in reply to Lu Bruce
    TI__Expert 4285 points

    HI Bruvin, 

    I understood that the requirement is 

    1. All packets from FPGA needs to go to the PHY connected to PORT 1 (RGMII1)

    2. All packets from arriving at PORT 1 needs to go to the Eth driver and should not go to RGMII2.

    Let me check how this can be done. This would be done with the help of correct policier configurations.

    Regards,

    Aswin

  • 0 in reply to Aswin Sankar
    TI__Expert 4285 points

    Hi Bruvin, 

    Meanwhile please review this proposal.

    If we can control the desintation address of the packets being send to PORT 1 and PORT 2, then we can enforce an ALE configuration based on mutlicast addresses.

    That is we can configure certain packets with a particular multicast address to go to Eth driver (host port) only and certain packets with a particular multicast address to go to the next port (PORT1 in this case) without going to the Eth driver (host port).

    Regards,

    Aswin

  • 0 in reply to Aswin Sankar
    Prodigy 20 points

    Hi Aswin,

    Yes, those are exactly the two requirements mentioned above.

  • 0 in reply to Aswin Sankar
    Prodigy 20 points

    Hi Aswin,

    For this proposal, is the unicast address not applicable?

  • 0 in reply to Lu Bruce
    TI__Expert 4285 points

    Hi Bruvin,

    Unknown unicast packets will be switched to other port. Also there is an option to send unknown unicast packet to host as well, this needs to be configured.

    Regards,

    Aswin

  • 0 in reply to Aswin Sankar
    Prodigy 20 points

    Hi Aswin,

    Please confirm the following requirements:

    1. If the FPGA sends a data packet with a unicast address to PORT2(RGMII2), will the data packet be sent to the Eth Driver or PORT1(RGMII1)?

    2. If the Eth Driver sends a data packet with a unicast address to PORT1(RGMII1), will the data packet be sent to the PHY?

    Best Regards,

    Bruvin

  • 0 in reply to Lu Bruce
    TI__Expert 4285 points
    Lu Bruce said:
    If the FPGA sends a data packet with a unicast address to PORT2(RGMII2), will the data packet be sent to the Eth Driver or PORT1(RGMII1)?

    Would this be the mac address of AM261 or the address of a different device ?

    If this is the address of a different device then the packet will go to PORT 1 and not Eth driver.

    Lu Bruce said:
    If the Eth Driver sends a data packet with a unicast address to PORT1(RGMII1), will the data packet be sent to the PHY?

    Yes this will happen as this is the default behaviour.

    Please note that, how the packet is routed is entirely based on the packet's desintation address. Not on ingress port number. ALE configuration rules will use the destination address as the matching criteria.

    Please let me know if this fulfills the requriement.

    Regards,

    Aswin

  • 0 in reply to Aswin Sankar
    Prodigy 20 points

    1. The mac address of a different device, not AM2612. 

    2. I think that only multicast or broadcast addresses need to configure ALE to filter messages, while unicast addresses will be routed to the terminal based on the destination address, right?

    3. If the second item is fulfilled, then the requirement can be satisfied.

    4. By the way, If the source address and destination address of the Ethernet data sent by the FPGA are consistent with the data sent by the ETH DRIVER, can the data sent by the FPGA be sent to the PHY through PORT1?

    Best Regards,

    Bruvin