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Original question:

AM2634: How to debug with multi cores

AM2634: How to debug multi core demo using XDS110

Wei Yao
Prodigy 140 points
Part Number: AM2634
Other Parts Discussed in Thread: AM2632

I had successfully debuged the ipc_notify_echo_am263x-lp_system_freertos_nortos demo with luanchpad.image.png

But There is error when I debug this demo with our own board with XDS110. You can see below picture.

image.png

  • 0
    TI__Expert 5906 points

    Hi,

    Could you confirm the part number of the device on your board?

    Thanks,

    Sahana

  • 0
    Prodigy 140 points

    Below is GEL output

    Cortex_R5_0: ***OnTargetConnect() Launched***

    Cortex_R5_0: AM263x Initialization Scripts Launched.
    Please Wait...


    Cortex_R5_0: AM263x_Cryst_Clock_Loss_Status() Launched
    Cortex_R5_0: Crystal Clock present
    Cortex_R5_0: AM263x_SOP_Mode() Launched
    Cortex_R5_0: SOP MODE = 0x0000000B
    Cortex_R5_0:
    Dev boot mode
    Cortex_R5_0: AM263x_Read_Device_Type() Launched
    Cortex_R5_0: EFuse Device Type Value = 0x000000AA
    Cortex_R5_0: AM263x_Check_supported_mode() Launched
    Cortex_R5_0:
    mode = 1
    Cortex_R5_0: MSS_CTRL Control Registers Unlocked
    Cortex_R5_0: MSS_TOP_RCM Control Registers Unlocked
    Cortex_R5_0: MSS_RCM Control Registers Unlocked
    Cortex_R5_0: MSS_IOMUX Control Registers Unlocked
    Cortex_R5_0: TOP_CTRL Control Registers Unlocked
    Cortex_R5_0:

    *** R5FSS0 DualCore Reset ***
    Cortex_R5_0:

    *** R5FSS1 DualCore Reset ***
    Cortex_R5_0: R5F ROM Eclipse
    Cortex_R5_0: R5FSS0_0 Released
    Cortex_R5_0: R5FSS0_1 Released
    Cortex_R5_0: R5FSS1_0 Released
    Cortex_R5_0: R5FSS1_1 Released
    Cortex_R5_0:

    All R5F Cores Released for program load
    Cortex_R5_0: L2 Mem Init Complete
    Cortex_R5_0: MailBox Mem Init Complete
    Cortex_R5_0: *********** R5FSS0/1 Dual Core mode Configured********
    Cortex_R5_0: CORE PLL Configuration Complete
    Cortex_R5_0: PER PLL Configuration Complete
    Cortex_R5_0: SYS_CLK DIVBY2
    Cortex_R5_0: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
    Cortex_R5_0:
    CLK Programmed R5F=400MHz and SYS_CLK=200MHz
    Cortex_R5_0:

    *** Enabling Peripheral Clocks ***
    Cortex_R5_0: Enabling RTI[0:3] Clocks
    Cortex_R5_0: Enabling RTI_WDT[0:3] Clocks
    Cortex_R5_0: Enabling UART[0:5]/LIN[0:5] Clocks
    Cortex_R5_0: Enabling QSPI Clocks
    Cortex_R5_0: Enabling I2C Clocks
    Cortex_R5_0: Enabling TRACE Clocks
    Cortex_R5_0: Enabling MCAN[0:3] Clocks
    Cortex_R5_0: Enabling GPMC Clocks
    Cortex_R5_0: Enabling ELM Clocks
    Cortex_R5_0: Enabling MMCSD Clocks
    Cortex_R5_0: Enabling MCSPI[0:4] Clocks
    Cortex_R5_0: Enabling CONTROLSS Clocks
    Cortex_R5_0: Enabling CPTS Clocks
    Cortex_R5_0: Enabling RGMI[5,50,250] Clocks
    Cortex_R5_0: Enabling XTAL_TEMPSENSE_32K Clocks
    Cortex_R5_0: Enabling XTAL_MMC_32K Clocks
    Cortex_R5_0:

    ***All IP Clocks are Enabled***

    Cortex_R5_0: CPU reset (soft reset) has been issued through GEL.

  • 0 in reply to Sahana H G
    Prodigy 140 points

    The part number is AM2632 on your board. Does it mean we can only use two core?

  • +1 in reply to Wei Yao
    TI__Expert 5906 points
    Wei Yao said:
    The part number is AM2632 on your board. Does it mean we can only use two core?

    Yes, that is correct. And you would be able to use R50-0 and R51-0 in that case. R50-1 and R51-1 would not be available.

    Regards,

    Sahana