AM6422: Freertos CPSW SWITCH 1588

Please correct the PHY model to DP83867.

Hi,

If you are referring to IEC 60870-104 protocol, then there will be no performance impact for the switching between external ports. But since IEC 104 is a TCP/IP based protocol, the maximum throughput that can be handled by the host port will be limited(this will not impact switching performance in any way). For more detailed performance metrics, you can refer to Performance Documentation. 

Coming to IEEE 1588, the protocol is supported by the hardware, but it is not supported in the SDK 8.6. The TSN support is enabled starting from 09.00 and enabled most of the additional support by 09.02. So, we would suggest to migrate to latest SDK preferably. If not, you can atleast move to 09.02 for fulfilling your requirements.

Please let us know if you have any further queries.

Regards,
Teja.

Hello，

    Thank you for your reply. Regarding the 1588 protocol, if we are on version 9.02, what is the specific name of the reference example we can look at? We will attempt to upgrade to version 9.02 first to use it.

Hello，

  Thank you for your reply. I discovered the enet_layer2_multi_channel project in the SDK 9.2 development package. Is this a 1588 example? How is this example related to the ones you mentioned? I'm a beginner in this area and hope you can help me differentiate and understand. After running enet_layer2_multi_channel on the board, I encountered errors as shown below. According to my usage scenario, which one do you think is the most suitable? Another question: my Linux environment's network card does not support hardware timestamping. Are there other methods to implement it? For example, using a software timestamping approach. The first step for me is to understand the entire time synchronization process; precision is not the main concern for now.

I have also discovered an issue: on the SDK 9.2 version, the project gptp_lwip_cpsw encounters errors during compilation. The main error is that there are two linkcmd files—one in the project path and another in the syscfg path. How should this error be resolved?

Hi,

It is recommended to use the gptp examples since these have the IEEE 1588 enabled. the multichannel example doesn't have the complete implementation of the IEEE 1588. 

Coming to the compilation errors in 09.02, are you using CCS to compile the project? I am building the example in 09.02.01 through make command, and I am able to compile it without issues. Please try with the make command once, and meanwhile, I will check with 09.02.00 version as well. 

Please let me know your observation with 09.02.01 and we can go from there. 

Thanks and regards,
Teja.

Hi，

    Thank you very much for your prompt reply! I opened version 9.02 using CCS and encountered the following error during compilation. While compiling via the makefile works, my ultimate goal is to achieve simulation through CCS.

Hi,

I was able to reproduce this issue. But with building the example using make command, we are not experiencing this issue. I will check if this issue is fixed in later versions and try to bring a fix. If it is not fixed yet, I will update this thread with an expected fix version for this issue.

Regards,
Teja.

Hello，

    Yes, we are developing using CCS. We hope you can provide a solution to resolve this issue in the current version.

Hi,

Please give me 4 business days to share the patch. Please ping here if it gets beyond that time.

Thanks and regards,
Teja.

Hello，

    I tried it and the example compile without any issues in CCS.Thank you!

Hi,

Thanks for confirmation. Since there are no further queries on this, Can we close this ticket?

Regards,
Teja.

Yes，you can close this ticket.

Thank you!

Hello，

    A question occurred to us while using the system: when operating in CPSW Ethernet switch mode, is it feasible to use 1588 for time synchronization? If so, how should the corresponding timestamps be retrieved? Should they be taken from the two external Ethernet ports?

Hi,

We don't support the complete IEEE1588 suite, but we support IEEE 802.1 AS gPTP protocols with which you can achieve time synchronization. The timestamping can be done by the CPTS module on board, which will give hardware timestamps of the received packets and sent packets. The gPTP functionality is already integrated into the examples mentioned above.

If you need to retrieve them to your application level, then we would have to check that possibility with our development team. If you have a different stream of packets which you would like to timestamp other than the event messages (sync, peer delay req and response), then you can do it in your application level directly using our software APIs (IOCTLs).

Please let us know your requirement for your application so that we can help you with better suited methods to fit your requirement.

Thanks and regards,
Teja.

Hello，

    In our actual application, we need the CPSW to function as a switch. Within the system, there are multiple devices based on AM6422, and we aim to achieve system-wide time synchronization with microsecond-level accuracy. Additionally, one AM6422 needs to serve as the clock source and synchronize with a GPS module.

Can the examples mentioned above meet our requirements? Beyond hardware timestamping, we also require a software-level soft clock for time-keeping. How should this be implemented? Specifically, how should the CPTS be used?

At the same time, I have another question: When the CPSW functions as a switch and PTP is used for time synchronization, will there be a delay introduced for the other slave clocks in the system during processing? Since the CPSW itself has internal latency when operating as a switch, can this delay be compensated for within the PTP protocol?

Hello，

    The method we are considering should involve implementing PTP with CPSW as a boundary clock, meaning CPSW is used as a switch. Is it possible to configure one physical port as a slave clock to the upstream and another physical port as a master clock to the downstream?

Hi,

The IEEE 802.1AS spec have moved from boundary clock/transparent clock definition to endpoints and bridges. So, all the devices in the network will be in sync, as long as the distance is less than 7 hops from the global master. Does this meet your requirement?

What is the scale of devices we are expecting in the network?

Thanks and regards,
Teja.

Hello，

    Our system scale is uncertain. Currently, I have a question: when used as a CPSW switch, it only performs simple data forwarding and does not need to run the PTP protocol—is that correct? If our usage involves not only functioning as a switch but also running the PTP protocol, is it achievable?We are not very familiar with the PTP protocol over Ethernet, and we would appreciate your advice on this.

Could you provide an engineering example where CPSW functions as both a switch and supports PTP? Or how should we modify the existing project to implement this functionality? We would greatly appreciate your help. Thank you very much.

Hi,

wanglili 王 said:

when used as a CPSW switch, it only performs simple data forwarding and does not need to run the PTP protocol—is that correct?

Yes, you are correct. CPSW can be operated even without the gPTP protocol running in the device. But this configuration should not be used while other nodes in the system are gPTP nodes, unless this is an endpoint.

wanglili 王 said:

If our usage involves not only functioning as a switch but also running the PTP protocol, is it achievable?

Yes, our PTP offering has support to operate as a bridge node, which means, it can operate as switch and support gPTP.

Teja Rowthu said:

If you are looking to test only the layer 2 application, you can use gptp_cpsw_app in the path $(MCU_PLUS_SDK)/examples/networking/tsn/gptp_cpsw_app. (gPTP Documentation) 

If you are looking to test along with the LwIP stack along with the PTP sync, you can use gptp_lwip_cpsw in the path $(MCU_PLUS_SDK)/examples/networking/tsn/gptp_lwip_cpsw. (gPTP LwIP Documentation).

The examples mentioned here will demonstrate your required usecase. But I would like to re-iterate that these examples support IEEE 802.1 AS, but not the older IEEE 1588 spec. IEEE 802.1 AS (gPTP) supports higher accuracy than IEEE 1588. Please check from your side if this fits your requirement.

Thanks and regards,
Teja.

Hello，

    The two examples simply use CPSW as independent Ethernet MACs. We want to configure CPSW as a switch and then use PTP. How should we configure this in the existing examples? Do we need to modify the code in the examples? Also, regarding your comment: "If other nodes in the network are gPTP nodes and your device is only a pure forwarding device (and not an endpoint), do not configure it this way, otherwise it may cause synchronization path breakage or incompatibility." Does this mean that if I simply use it as a switch, the devices connected to the two physical ports cannot be other devices running PTP? Is my understanding correct?

Additionally, when using the switch to support both PTP and application processing such as the IEC 60870-5-104 protocol via the CPSW host port, is this feasible? In this scenario, are there any hop count limitations, such as the previously mentioned restriction of within 7 hops?

Hi,

wanglili 王 said:

 The two examples simply use CPSW as independent Ethernet MACs. We want to configure CPSW as a switch and then use PTP. How should we configure this in the existing examples?

The examples are indeed configured in switch mode. Did you encounter any issues while connecting the boards in switch configuration? The CPSW module is by design a switch, and it can be configured as MAC-only device if required. The SDK examples for gPTP + LwIP configure CPSW as switch.

I have verified the examples from the SDK to be in switch mode. If you connect multiple boards in daisy chain, you can observe that the boards would get in sync. Alternatively, if the board is connected between two gPTP enabled nodes, you can observe that all 3 nodes come into sync. 

wanglili 王 said:

 Does this mean that if I simply use it as a switch, the devices connected to the two physical ports cannot be other devices running PTP? Is my understanding correct?

Yes, if you connect gPTP nodes through non-gPTP supported switches, then the sync will not be possible due to the nature of sync mechanism. But the packet transmission will still continue without interruptions.

wanglili 王 said:

when using the switch to support both PTP and application processing such as the IEC 60870-5-104 protocol via the CPSW host port, is this feasible?

I am not very familiar with the IEC 60870-5-104 protocol, but based on the initial review, it is based on TCP/IP protocol. This should not effect the operation of gPTP, and gPTP wont effect the operation of IEC 60870-5 protocol. But I would advice you to run sanity check.

Thanks and regards,
Teja.

Hello，

    We further confirmed and found that the configuration defaulted to switch mode, which was an issue with our testing. Thank you for your detailed explanation.

    Now we understand this part, but there is another aspect we are unfamiliar with. If one of our devices uses GPS for time synchronization, should the PPS (pulse per second) signal from GPS be connected to CPTS? Will it automatically adjust the frequency based on the interval of the PPS signal? How is the corresponding phase adjusted? In practical use, we also need a software clock, which is typically maintained through a hardware timer. How can we ensure that the timer remains consistent with the frequency and phase after adjusting them via CPTS?

    We have two devices, both running this sample program. We connected physical port 1 of device 1 to physical port 1 of device 2. After running, we found that the network connection was not recognized. What could be the reason? Each device alone can be directly connected to a PC and is recognized.

Hi,

wanglili 王 said:

We connected physical port 1 of device 1 to physical port 1 of device 2. After running, we found that the network connection was not recognized.

Can you provide more details on the failure and attach the logs of both devices if possible? Please let us know the version of MCU+ SDK you are using to run the test and the specific example you are using for your testing. I can test this in our local test bench, and let you know the results.

Regards,
Teja.

Hi,

wanglili 王 said:

If one of our devices uses GPS for time synchronization, should the PPS (pulse per second) signal from GPS be connected to CPTS?

Yes, this is supported, but we do not have an example for this as of now. This can be done by having the PPS signal timestamped by CPTS, and adjusted with the GPS signal input. Both Phase and frequency has to be adjusted using this process, and it can be done by using software APIs. 

Even after applying the phase and frequency corrections to CPTS module, the clock cannot be said to be consistent since the differences in ticks will keep varying, and the adjustments should be made continuously. CPTS time stamps will give the corrected time output after we add the adjustments. Is there a requirement for you to access the actual hardware ticks without the adjustments? Please let us know why this is used so that we can understand this usecase, and suggest possible solutions

Thanks and regards,
Teja.

Hello,

    Apologies for not seeing your reply in time due to the holiday. Our test setup consists of two AM6422 devices, both using the CPSW Ethernet switch mode. One Ethernet port of each device is connected via a network cable, and both are running the gPTP example program. In this scenario, we found that there is no physical link (PHY link). However, when each device is individually connected to a PC via Ethernet, it works fine. The printed messages are as follows. We hope you can help analyze the specific cause and provide assistance.

Hi 

Can you please confirm the ports that you are using to connect the boards with each other? Please refer to the example documentation for the hardware connections. We are able to run this example with 2 boards connected to each other. Please also mention the exact example that you are flashing on the evm, so that we can test the same setup. 

Regards,
Teja.

Hello，  

    The example we used is at path $(MCU_PLUS_SDK)/examples/networking/tsn/gptp_lwip_cpsw. Both boards are connected to port 1 of the CPSW switch via a direct Ethernet cable. The boards we are using are not EVM boards but our own custom-designed ones. However, when connecting each board individually to a PC, there is no issue—they can ping successfully, and connecting them to a switch also works fine.

Hello,

    The PHY we are using is the DP83867, which actually supports gigabit speeds, but our hardware does not. We conducted a test: when both devices were running RTOS, there was no Ethernet connection. However, when one of the devices was switched to a Linux system, the network port established a connection, but the following message appeared. We suspect this might be an issue specific to RTOS.
[ 62.389172] TI DP83867 8000f00.mdio:01: Downshift occurred from negotiated speed 1Gbps to actual speed 100Mbps, check cabling!
[ 62.391619] am65-cpsw-nuss 8000000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off

Hello，

    The issue with the two devices not linking has been resolved. The problem was that our hardware does not support Gigabit speeds, but during auto-negotiation, the PHY attempted to negotiate at Gigabit, which caused the failure. We disabled the Gigabit advertisement, forcing auto-negotiation to 100Mbps, and everything returned to normal.

    We have a concern that is important to us. Our products are mainly used in power systems. The gPTP time synchronization in the example should not be exactly the same as 1588 time synchronization. Our system also needs to connect with other products that support 1588 but may not support gPTP. In such cases, can synchronization still be achieved?

    Additionally, regarding gPTP time synchronization, we need to obtain the absolute time of the software clock, such as year, month, day, hour, minute,  second and microsecond ,and then record software timestamps under certain special circumstances. This software clock is typically maintained by a timer. However, how can this timer be associated with gPTP time synchronization to ensure frequency and phase alignment? We hope to receive your technical support on this matter.

Hi,

We will check with the 09.02 SDK release example, and let you know the details. This functionality has been tested with the latest releases, and found to be working. Since I would be in business travel next week, please expect some delay in responses.

Thanks and regards,
Teja.

Hi,

Thank you for your update. This resolves the connection issues. The details provided about the project helps a lot to understand the context of the implementation. 

wanglili 王 said:

Our system also needs to connect with other products that support 1588 but may not support gPTP. In such cases, can synchronization still be achieved?

Although few implementations of IEEE 1588 PTPv2 and gPTP can sync in a network, they are not directly compatible. The hardware available in CPSW is capable of IEEE 1588 PTP. So, if you can implement the software stack to handle 1588 PTP traffic, you should be able to achieve sync. But currently, TI doesn't offer support for 1588. You can use PTP daemon which supports IEEE 1588 PTPv2 with LwIP and FREERTOS configuration available (open source). Alternatively, you can contact with 3P to get the implementation. 

Regarding the software time, you would have to use the data from the GPS modules which will communicate the current time along with PPS. You can use the on-board time keeping timer to sync with the GPS module to also calculate the current time.

In my opinion, testing for the IEEE 1588 PTP would be more critical than maintaining the software clock.

Please let us know if you have any queries regarding this.

Thanks and regards,
Teja.

Hello,

    If we develop the 1588 PTPv2 ourselves, does the CPSW Ethernet switch have the functionality of a boundary clock? Could you provide some relevant assistance, such as relatively mature protocol stack code or similar resources?

Hi,

CPSW hardware is compatible to support IEEE 1588 spec with its hardware based timestamping. You can use either Layer-2 or Layer-3 based implementations to achieve this. Currently, I will have to check with the resources once to suggest you. Please expect delayed responses since I am currently in business travel.

Thanks and regards,
Teja.

Hello，

    The gptp example uses the CPSW switch mode. If only using a single Ethernet port connected to a switch that supports the gptp protocol, is this example still applicable? What configuration changes need to be made?

Hi,

Yes, the example is still applicable. No additional changes are needed, and the example will automatically detect the best master clock, and sync to it. This is similar to connecting only one port of the board to another gPTP node (host PC or another board). 

Please let us know if you have further queries.

Regards,
Teja.

Hi,

Regarding the 1588 open source stacks available, you can consider PTPd (PTP daemon) since it is one of the widely used options available. Alternatively, if you are open to approach 3rd party suppliers, you can reach out to 3P vendors like Exelfore to enable 1588 stack on freertos+lwip.

Regards,
Teja.

Hello，

    If using CPSW as two independent MACs, with port0 serving as the gPTP protocol slave clock and port1 not participating in the gPTP protocol, but both connected to a switch that supports the PTP protocol, is it possible to use them in this way?Do we need to configure this part in sysconfig?

Hi,

Yes, this is possible, and it needs changes in the sysconfig and in the application level. We have to disable the switching, and enable mac-only mode using syscfg-gui. We have to config the application to work with only one macport to run the gPTP stack. 

Regards,
Teja.

Hello，

    Regarding the modification of this part, could you provide some reference methods for the changes? Thank you very much！

Hi,

By updating the sysconfig fields, you can enable MAC-only mode: Ale Config -> ALE Port config -> MAC Only mode config -> hostport/macport1&2 -> enable mac-only mode: set to enable.

By modifying the structure available here, you can include/exclude the macport from the PTP stack: EnetApp_initAppCfg() in enetapp_cpsw.c

Regards,
Teja.