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AM6441: restrict , force to use 32-bit instruction for A53

Jun Tu
Expert 1720 points

Part Number: AM6441

Hi, 

nvironment.

We are using GPMC for memory access. Our question is: is the GPMC forced to operate in 32-bit mode on the A53?

When we attempt to read a 64-bit value from a GPMC-mapped memory region, the read fails and returns corrupted data. For example:

x2 = 0x52000000
ldr x1, [x2 + 0x18000]   // reading 64-bit value fails, exception, bus is not allowed

We are considering solutions such as:

  • Using compiler options to force 32-bit (w1, w2) accesses instead of 64-bit (x1, x2) registers.

  • Determining the proper method to read 64-bit values from GPMC without corruption.

What is the recommended approach to reliably access GPMC memory in this scenario?


 

  • +1
    TI__Guru 54068 points

    Hello Jun Tu,

    The GPMC on AM64x is a 32-bit bus interface. When the Cortex-A53 processor (running in AArch64 mode) executes a 64-bit load instruction such as:

    ldr x1, [x2, #0x18000] // 64-bit load - WILL FAIL . This generates a 64-bit bus transaction. The GPMC cannot service 64-bit transactions, resulting in bus errors and data corruption.


    Recommended Solution :

    Use explicit 32-bit volatile pointer accesses for all GPMC memory operations. Do not use compiler options to force
    32-bit mode — instead, use properly typed read/write operations:

    /* Reading from GPMC-mapped memory */
volatile uint32_t *pSrc = (volatile uint32_t *)(offset + baseAddress);
volatile uint32_t *pDst = (volatile uint32_t *)buf;
*pDst = *pSrc;

/* Writing to GPMC-mapped memory */
volatile uint32_t *pSrc = (volatile uint32_t *)buf;
volatile uint32_t *pDst = (volatile uint32_t *)(offset + baseAddress);
*pDst = *pSrc;

    Regards,

    Anil.