• State Resolved
  • Locked Locked
  • Replies 11 replies
  • Answers 2 answers
  • Subscribers 31 subscribers
  • Views 453 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMDSCNCD263P: Issue with placing .bss, .stack, and .sysmem in TCMA or TCMB1 on AM263Px – triggers HwiP_user_data_abort_h...

AM263P4: The operating modes of the AM263P cores.

O.H
Mastermind 7170 points

Part Number: AM263P4
Other Parts Discussed in Thread: SYSCONFIG, UNIFLASH, AM2631, AM263P2

Hi experts,

Below are our questions regarding the operating modes of the AM263P cores.
The following diagram shows the operating modes as we currently understand them.

Operating Mode R5F0 CORE0 R5F0 CORE1 R5F1 CORE0 R5F1 CORE1 Clustered Memory
Lock Step Mode (Max TCMA/TCMB) Operates (64KB/192KB max) Lock Step Operation Not Available Not Available Unified
Single Core Mode (Max TCMA/TCMB) Operates (64KB/192KB max) Halted Not Available Not Available Unified
Split Lock Step Mode (Max TCMA/TCMB) Confirmation Required (*1) Confirmation Required (*1) Confirmation Required (*1) Confirmation Required (*1) Split
Dual Core Mode (Max TCMA/TCMB) Operates (32KB/96KB max) Operates (32KB/96KB max) Operates (32KB/96KB max) Operates (32KB/96KB max) Split

*1: Confirmation Required” indicates items that cannot be verified at present based on the TRM or publicly available documents.

Q1: Does our understanding of Single Core Mode shown above match the actual definition?
If it is correct, are there any sample programs (such as SBL) or procedural documents available for using this mode?

Q2: In the thread referenced below, the term “Split Lockstep Mode” is used. Does this term have the same meaning as “Split Core Mode” or “Dual Core Mode” described in the TRM?
If not, could you explain how “Split Lockstep Mode” differs from the other modes?
(+) TMDSCNCD263P: Issue with placing .bss, .stack, and .sysmem in TCMA or TCMB1 on AM263Px – triggers HwiP_user_data_abort_handler_c - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums 

Q3: To ensure a stable evaluation environment, could you provide any recommended version combinations for the following software?

  • CCS (Eclipse / Theia)
  • SysConfig
  • Uniflash
  • Python (Python itself and required pip package versions)
  • OpenSSL

Based on the responses from Mr. Anand in the thread above, it appears that different versions of each software were used together. From this, we suspect that certain version combinations may impact stability. We would like to fix our evaluation environment to ensure reproducibility, so we would appreciate clarification on this point.

Best regards,
O.H

  • 0
    TI__Guru 60080 points

    Hi OH,

    O.H said:
    Lock Step Mode (Max TCMA/TCMB) Operates (64KB/192KB max) Lock Step Operation

    I have mentioned it in the previous thread as well, Lockstep mode is the same as Single core mode - Where R5F0Core 1 is in lockstep mode.

    O.H said:
    Split Lock Step Mode (Max TCMA/TCMB) Confirmation Required (*1) Confirmation Required (*1) Confirmation Required (*1) Confirmation Required (*1) Split
    Dual Core Mode (Max TCMA/TCMB) Operates (32KB/96KB max) Operates (32KB/96KB max) Operates (32KB/96KB max) Operates (32KB/96KB max) Split

    Split lock(step) mode is same as Dual core mode 

  • 0
    TI__Guru 60080 points
    O.H said:
    If it is correct, are there any sample programs (such as SBL) or procedural documents available for using this mode?

    Single core mode is lockstep mode, i.e single core is available for program execution and the other core is in lockstep mode. As mentioned before, you can configure different modes using sbl syscfg.

    Please refer to the previous e2e.

  • 0 in reply to Nilabh Anand
    TI__Guru 60080 points
    O.H said:

    Q3: To ensure a stable evaluation environment, could you provide any recommended version combinations for the following software?

    • CCS (Eclipse / Theia)
    • SysConfig
    • Uniflash
    • Python (Python itself and required pip package versions)
    • OpenSSL

    Based on the responses from Mr. Anand in the thread above, it appears that different versions of each software were used together. From this, we suspect that certain version combinations may impact stability. We would like to fix our evaluation environment to ensure reproducibility, so we would appreciate clarification on this point.

    Please refer to the sdk release notes to find the exact tools and compiler versions to use:

    https://software-dl.ti.com/mcu-plus-sdk/esd/AM263PX/latest/exports/docs/api_guide_am263px/RELEASE_NOTES_11_01_00_PAGE.html#autotoc_md237

    All the SDK releases are tied and tested to a specific version of dependent tools. You can refer to the same in the release notes of any release you are planning to use.

    It is recommended to use the latest versions when you start development.

  • 0 in reply to Nilabh Anand
    TI__Guru 60080 points

    For open ssl and python version refer to this:

    software-dl.ti.com/.../SDK_DOWNLOAD_PAGE.html

  • 0 in reply to Nilabh Anand
    Mastermind 7170 points

    Hi ,

    Thank you for your support.

    Additional question for core mode.

    Q4: Is my understanding correct that, among the SBL sample projects, only the “Null” SBL operates in Dual Core Mode (syscfg = standalone), and all other SBL variants are expected to operate in Lockstep Mode?

    Q5: If I want to run only R5F0-0, is the correct procedure to boot in Dual Core Mode and then place all other cores into WFI?
    If there is any documentation that describes this procedure, could you please point me to it?

    Nilabh Anand said:
    Single core mode is lockstep mode, i.e single core is available for program execution and the other core is in lockstep mode. As mentioned before, you can configure different modes using sbl syscfg.

    Q2-2:Do you have any official documentation from TI that describes the procedure, rather than only the responses provided on E2E?
    I believe the document below may correspond to that purpose, but if there is any more detailed.
    Secondary Bootloader flow in AM26x devices — AM26x Academy
    AM263Px MCU+ SDK: Understanding the bootflow and bootloaders

    Best regards,
    O.H

  • 0 in reply to O.H
    Mastermind 7170 points

    Hi ,

    Could you please explain how to configure the device into the Single Core Mode shown in the diagram below?

    In the TRM, Single Core Mode and Lockstep Mode are described as different operating modes,
    but in your response, these two modes were treated as the same.
    This inconsistency is causing confusion.

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Guru 60080 points

    Thank you for the clarification, let me confirm with our design team, just to be double sure,

  • 0 in reply to Nilabh Anand
    TI__Guru 60080 points

    Hi OH,

    I just received more details from our design team, they have confirmed that there is no single core mode separately, This is a miss in the trm, I will take action to get this corrected.

    This was valid for AM263x (predecessor device), which had a single core variant i.e only one core was active in the cluster, second core was non-operational.

    The same is not applicable for AM263Px.'

    Let me know if there are any other clarification needed.

  • 0 in reply to Nilabh Anand
    Mastermind 7170 points

    Hi Nilabh Anand,

    Thank you for your reply.

    Nilabh Anand said:

    I just received more details from our design team, they have confirmed that there is no single core mode separately, This is a miss in the trm, I will take action to get this corrected.

    This was valid for AM263x (predecessor device), which had a single core variant i.e only one core was active in the cluster, second core was non-operational.

    The same is not applicable for AM263Px.'

    I understood. So could you please tell me how to achieve the same single-core operation as the AM2631 with the AM263P? Q5 method?

    I would also appreciate comments on Q2-2 and Q4.

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Guru 60080 points
    O.H said:
    I understood. So could you please tell me how to achieve the same single-core operation as the AM2631 with the AM263P? Q5 method?

    One fundamental difference is that AM2631 has only one core present , where as there is no such part number as AM263P1. I am assuming you are planning to use AM263P2, so to get same operation , You need to just load the application for Core 1, and do not load application on the second core.

  • +1 in reply to O.H
    TI__Guru 60080 points
    O.H said:
    Q4: Is my understanding correct that, among the SBL sample projects, only the “Null” SBL operates in Dual Core Mode (syscfg = standalone), and all other SBL variants are expected to operate in Lockstep Mode?

    It is completely up to the user how they want the cores to be configured; all sbls are for reference purposes only. 

    O.H said:
    Q2-2:Do you have any official documentation from TI that describes the procedure, rather than only the responses provided on E2E?
    I believe the document below may correspond to that purpose, but if there is any more detailed.
    Secondary Bootloader flow in AM26x devices — AM26x Academy
    AM263Px MCU+ SDK: Understanding the bootflow and bootloaders

    The configuration itself is done by writing to the R5F lockstep register; SBL just enables that. You can refer to the TRM for AM263Px for the same.

    O.H said:

    Q5: If I want to run only R5F0-0, is the correct procedure to boot in Dual Core Mode and then place all other cores into WFI?
    If there is any documentation that describes this procedure, could you please point me to it?

    Yes this is correct. Please refer to the TRM for the same. 

    (Register Addendum)

    (TRM)