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AM261-SOM-EVM: AM261x Intercore Ethernet Packet Exchange

Vasil Hristev
Prodigy 70 points

Part Number: AM261-SOM-EVM
Other Parts Discussed in Thread: AM2612

Hello!

I have a use case in which I want to exchange ethernet packets between r5fss0-0 and r5fss0-1 cores via  LwIP software bridge. I checked that TI provides such SDK example for AM64x micros (Intercore Ethernet Packet Exchange With ICSSG, Using LwIP Bridge ). I see that this is present in AM64x MCU+ SDK 11.02.00.

I checked the AM261x SDK and noticed that part of this example is there (\source\networking\enet\core\examples\lwip\enet_intercore_icssg), but it is not completed. Does TI plan to finish the implementation of this example in some of the next releases of the SDK?

  • 0
    TI__Guru 59270 points

    Hi Vasil,

    this is currently not planned for the upcoming sdk releases. Also the icssg is not present on AM261x, only icssm(100Mbps) is present.

  • 0 in reply to Nilabh Anand
    TI__Guru 59270 points
    Vasil Hristev said:
    I checked the AM261x SDK and noticed that part of this example is there (\source\networking\enet\core\examples\lwip\enet_intercore_icssg), but it is not completed

    It is present because the enet repo is common across the MCU SDKS, thus the folder got packaged.

  • 0 in reply to Nilabh Anand
    Prodigy 70 points

    Hi Nilabh,

    thanks for the info! Do you know if it is technically feasible to achieve something similar using cpsw. Even though there is no such example in the SDK, does it have what is needed to construct it myself? I see that some of the modules are present (bridgeif, lwip_ic, etc...), I just want to confirm I have what I need before digging further into this.

  • 0 in reply to Vasil Hristev
    TI__Guru 59270 points

    Hi Vasil,

    While it is feasible, I think that this approach for sharing data across the core is memory-intensive for am261x, as you will have additional lwip code which is redundant.

    I would like to understand the motivation for the same

  • 0 in reply to Nilabh Anand
    Prodigy 70 points

    Hi Nilabh,

    my use-case is the following. Core1 of the AM2612 micro will handle communication with the external world. It will initialize and configure the communication peripherals, run the comm stack, etc... Core 0 will run the product specific logic. However some of the communication packets have to be routed to core 0 (it will implement one server component). Because of that we though that the architecture above is suitable for routing the relevant data for core 0 from core 1.

  • 0 in reply to Vasil Hristev
    TI__Guru 59270 points

    Understood, is it possible that core0 can access the packets without overhead of the stack to process the data, if no then I believe that your approach would be best suited.