• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 32 subscribers
  • Views 216 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2612: Is the RTI counter 64 bit ?

Hideaki Matsumoto
Genius 9765 points

Part Number: AM2612
Other Parts Discussed in Thread: SYSCONFIG,

Hi,

My customer has some questions about RTI. Could you answer to their questions below ?

They want to get the value of the free-run counter of RTI, so they are thinking to use RTI_counterGet included in the SDK.

In the TRM, there is a 64-bit counter block, and the SDK also has counterLow and counterHigh.

Therefore, they tried to combine counterLow and counterHigh, but it became abnormal value.

If only counterHigh is extracted, it will be a normal value.

 

< Questions >

  1. Is it correct to assume that RTI is 64-bit? (If you look at the contents of the SDK, it looks as if it is just reading the 32-bit free-run counter with counterHigh.) 
  2. What are the meanings of CSL_RTI_RTIFRC0 and CSL_RTI_RTIUC0 ?
  3. The offset address of the register is listed in cslr_rti.h, but the TRM did not tell which register has what meaning. Which materials can they look at ?

From TRM,

TRM.jpg

 

From SDK

SDK.jpg

 

From cslr_rti.h

cslr.jpg

 

Thanks and regards,
Hideaki

 

 

 

  • 0
    TI__Mastermind 22162 points

    HI Matsumoto-san,

    In each RTI Instance, there are Two 64-bit counter blocks (counter block0 and counter block1). Each block has the following.

    1. One 32-bit up counter.
    2. One 32-bit free running counter.
    3. Two capture registers - Pre-scale and free running counter capture for special events.
    Hideaki Matsumoto said:
    Is it correct to assume that RTI is 64-bit? (If you look at the contents of the SDK, it looks as if it is just reading the 32-bit free-run counter with counterHigh.) 

    The whole block is 64-bit, internally, there are two 32-bit counters (FRC and UC)

    Hideaki Matsumoto said:
    What are the meanings of CSL_RTI_RTIFRC0 and CSL_RTI_RTIUC0 ?

    Since each RTI instance has two blocks, and each block will have two 32-bit counters, you will have UC0, FRC0 (block-0) and UC1, FRC1 (block-1). The UC increments every RTI Clock cycle and once it matches the configured compare value, the FRC will be incremented and UC will be reset back to 0 and start counting up again.

    For example, The Up counter increments every 1 FCLK clock cycle. Which means, if your Clock to the RTI module is 200Mhz then the UC will increment for every 50ns. The FRC ONLY updates if the UCx matches the UP counter Compare value. The FRC is pre-scaled by the UC0. Which means, every time UC0 reaches the Compare up counter value, FRC is incremented by 1, which means for every 10,000 ticks FRC is incremented by 1 tick.

    Hideaki Matsumoto said:
    The offset address of the register is listed in cslr_rti.h, but the TRM did not tell which register has what meaning. Which materials can they look at ?

    You can look at the register addendum for register level details: https://www.ti.com/lit/ug/spruj94a/spruj94a.pdf?ts=1769076208613&ref_url=https%253A%252F%252Fwww.google.com%252F

    To understand the RTI In depth, you can refer to this AM26x cademy module: https://dev.ti.com/tirex/explore/node?isTheia=false&node=A__AcevDJsanUk7IY6EafZ8ZA__AM26X-ACADEMY__t0CaxbG__LATEST

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    TI__Genius 9765 points

    Hi Shaunak,

    Thank you for your answers. That’s helpful. The customer generally understood, but they want to confirm the following your comment.

    Shaunak Deshpande said:
    which means for every 10,000 ticks FRC is incremented by 1 tick.

      

    Could you check below  if their understanding is correct ?

      

    They configured with SysConfig like below.

     

    Input Clock Frequency : 25MHz

      => UC is incremented by 40ns

      

    Desired Output Frequency : 1MHz

      => The compare value of Up Counter is internally set as “25” and FRC is incremented when UC reached in “25”.

      => FRC is incremented by 1us.

       

    The above their understanding is correct ?

     

    Thanks and regards,

    Hideaki

  • 0 in reply to Hideaki Matsumoto
    TI__Mastermind 22162 points

    HI Matsumoto-san,

    1. At input clock of 25MHz , the UC will increment by 40ns, this is correct

    2. When output freq is 1MHz, the UC counter value is internally set Compare Up Counter register value to 25-1 = 24 (as the counting starts from 0 to 24) (syscfg will automatically handle this calculation)

    3. When the counter value reaches 24 and it compares to the value in the compare up register, the FRC Is incremented by 1us (since output freq was 1MHz)

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    TI__Genius 9765 points

    Hi Shaunak,

     

    Thank you so much for your answers. The customer would like to confirm a little bit more.

     

    Their understanding is that there is not the feature which automatically clear the free run counter at the timing of occurring Compare Event. Is this correct ?

    If they want to clear the free run counter, is there any way other than clearing by the API of counter clear by enabling a interrupt ?

     

    They’re replacing Renesas MCU with AM2612, and considering to implement the TPU function of Renesas device by using RTI on AM2612.

    TPU has the register which can be set to clear a counter by compare match, but they cannot find a similar feature on RTI.

    This is the reason why they’re asking about the above question.

     

    TPU (Time Pulse Unit) has Compare Match Interrupt.

    Compare Match Interrupts : An interrupt can be generated when the timer counter matches a specific set value in the Timer General Register (TGR), allowing for precise timing of software events.

     

    Thanks and regards,

    Hideaki

  • 0 in reply to Hideaki Matsumoto
    TI__Mastermind 22162 points

    Hi Matsumoto-San,

    Let me check this with our hardware team and get back.

    Regards,
    Shaunak

  • +1 in reply to Shaunak Deshpande
    TI__Mastermind 22162 points

    Hi Matsumoto-san,

    If i understand your requirement correctly, You want the FRC counter to be auto-cleared when the compare event occurs Is this correct?

    If yes, the AM261x does not have auto-clear for the FRC counter. The UC counter counts up from 0 to the match value and then gets auto-reset to zero while FRC will be incremented by 1, but in no compare event will the FRC be auto-cleared or reset to 0.

    This has to be done manually through software:

    But if you just clear FRC without stopping the other counters, there will be inconsistencies, so the recommended approach would be to stop the counters, clear them and then resume the counters again

    If you want to clear all the RTI Counters, call the API: 

    int32_t RTI_counterClear(uint32_t baseAddr, uint32_t cntIndex)
    Regards,

    Shaunak