• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 254 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM6411: TI Recommendation about AM64x

Jimmy Huang
Genius 3985 points

Part Number: AM6411

Hello:

The customer project has MCU/MPU requirements, and it seems that TI's AM64x is more suitable, so we would like to ask TI to carefully evaluate it. Does it meet the following requirements:
hardware system 
-Control 20 SPI DAC chips (<100us delay), requiring RPU master control
-Can RPU control 8 ADC chips (<100us delay)?
-Gigabit Ethernet
- PCIe Gen2/3 x1 (EP)
-Other low-speed peripherals
-Common requirements for embedded Linux systems (APU, DDR, MMC/QSPI flash)
firmware driver
-Does RPU support SMP?
-Does MCSPI's 4 chip selection support DMA (without RPU chip selection)?
-Does PCIe EP have Linux driver support?
-Is there a mature driver for communication between APU and RPU?
-Does it support independent operation of RPU (APU reset does not affect RPU operation)?
-Does RPU support ZephyrRTOS?

Thanks!!!

  • 0
    Genius 3985 points

    Hello:

    Any updated?

  • 0 in reply to Jimmy Huang
    TI__Guru 53978 points

    Hello Jimmy,

    Can you please clarify what RPU means here? Is it the PRU core or the R5F core?

    Regards,

    Anil.

  • 0 in reply to Swargam Anil
    TI__Guru 53978 points

    Hello Jimmy,

    Please look at my comments below .

    MCSPI Specifications on AM64x:

    - MCSPI Instances: 5 (MCSPI0 - MCSPI4)
    - Chip Selects (CS): 4 per instance (MCSPI_MAX_NUM_CHANNELS = 4)
    - Total Hardware CS: 5 × 4 = 20 CS available
    - DMA Support: Yes (UDMA)
    - Maximum SPI Clock: 50 MHz

    Theoretical Timing Estimation:

    - SPI Clock: 50 MHz (max)
    - 16-bit DAC write: 16 bits / 50 MHz = 0.32 µs per DAC
    - 20 DACs sequential: 20 × 0.32 µs = 6.4 µs (data transfer only)
    - CS switching overhead: ~0.1 µs per device
    - Total estimated: < 20 µs for all 20 DACs

    Note: These are theoretical calculations.

    Conclusion: The <100 µs requirement is achievable with RPU (R5F) control.


    R5F OPERATING MODE - AMP ONLY (NO SMP) :

    R5F cores do NOT support SMP mode. All R5F cores work in AMP (Asymmetric Multi-Processing) mode only.

    In AMP Mode:
    - R5F Core 0 runs its own RTOS/bare-metal (independent)
    - R5F Core 1 runs its own RTOS/bare-metal (independent)
    - R5F Core 2 runs its own RTOS/bare-metal (independent)
    - R5F Core 3 runs its own RTOS/bare-metal (independent)

    Each core runs separate code independently. There is no shared OS scheduler across R5F cores.


    APU-RPU COMMUNICATION (IPC) :

    IPC Mechanism:
    - Used to transfer data between different cores
    - Supports APU (A53) to RPU (R5F) communication
    - Supports RPU (R5F) to RPU (R5F) communication

    Driver Status: This driver is already mature and many customers are using it in production.


    INDEPENDENT CORE OPERATION - RESET DOMAIN CLARIFICATION :

    AM64x Reset Domain Architecture:

    MAIN DOMAIN contains:
    - A53 (APU)
    - R5FSS0 (RPU) - Core0, Core1
    - R5FSS1 (RPU) - Core0, Core1

    Important: MAIN Domain Reset affects ALL cores in this domain. A53 AND R5F are reset together.

    MCU DOMAIN contains:
    - M4F Core

    Important: MCU Domain is ISOLATED from MAIN Domain. MAIN Domain Reset does NOT affect MCU Domain.

    Conclusion:

    - Independent APU/RPU (A53/R5F) reset is NOT supported. Both A53 and R5F are in MAIN domain. MAIN domain reset affects both cores.
    - MCU Domain (M4F) CAN operate independently. M4F can be isolated from MAIN domain. MAIN domain reset does NOT affect M4F. M4F continues running without disturbance.


    ZEPHYR RTOS SUPPORT STATUS :

    Current Status: NOT OFFICIALLY SUPPORTED

    - Basic Zephyr porting done on AM243x R5F
    - Not officially supported yet
    - Plans to support Zephyr this year

    Recommended Alternative: FreeRTOS is fully supported on R5F in MCU+ SDK

    Can you please share the details on why you want to use ZephyrRTOS rather than FreeRTOS on the R5F core?

    This will help us understand your requirements better and provide appropriate guidance.

    Pending Questions : 

    -Gigabit Ethernet
    - PCIe Gen2/3 x1 (EP)

    -Common requirements for embedded Linux systems (APU, DDR, MMC/QSPI flash)
    firmware driver

    I am routing your query to Linux experts .


    Regards,

    Anil.

  • 0 in reply to Swargam Anil
    TI__Guru**** 179621 points
    Swargam Anil said:

    Pending Questions : 

    -Gigabit Ethernet
    - PCIe Gen2/3 x1 (EP)

    -Common requirements for embedded Linux systems (APU, DDR, MMC/QSPI flash)
    firmware driver

    Linux on AM64x supports Gigabit Ethernet, PCIe Gen2 (not Gen3) in EP and RC modes. MMC/QSPI flash is also supported. Linux runs on DDR by A53, so APU and DDR are supported in Linux too.