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MSPM0G3519: MSPM0G3519: ADC conversion time

Khanh Doan
Intellectual 280 points

Part Number: MSPM0G3519

Hi Ti Team,

I working on ADC topic for my project (10 bit resolution). Currently I'm using ULPCLK 40Mhz, MCLK using SYSOSC with 32Mhz. Value of SCOMP0 = 2 and SCLKDIV = 3 => This will imply in total 8x2 = 16 sample clock cycle.

Then with configuration of FRANGE => It will take additional 8 cycle 

=> In total I think it needs around 24-25 ADC clock cycle.

My implementation is like following:

I start the ADC conversion, and the check the RIS in a while loop. There will be a timeout counter. This will be decreased everytime if check the RIS, and when it equals to 0 . It will break out the loop

If the RIS of MEM0 raises, this means the ADC conversion is completed and I can get the result.

My question is why the result is too fast? My timeout counter needs only 2 decrease value to receive the RIS flag. So I guess my calculation is not correct ?

How can I calculate the conversion time of the ADC ?

  • +1
    TI__Genius 12315 points

    Hi Khanh,

    The way you are calculate ADC conversion time (include both sampling time and conversion time) looks fine for me.

    I have two comments here:

    #1 The clock configuration "ULPCLK = 40MHz, and MCLK = SYSOSC = 32MHz" is not achievable because MCLK will always be equal or higher than ULPCLK. 

    #2 In the while loop polling ADC conversion result, you are using a software counter variable right? Because in a while loop cycle, the CPU actually have multi instructions to run, such as check while condition, read RIS register value, take add operation on counter variable, so it take time for a while loop cycle. Assume you are using 32MHz ADC clock, a 25 ADC clock cycle is around  0.78us, it is a short time and I think the counter value of 2 is possible in this case.  

    Best Regards,
    Pengfei

  • 0 in reply to Pengfei Xie
    Intellectual 280 points

    Yes, I'm using a software counter. Thank you for your response.