AM2434: interrupt-occurence when using IPC with MAIN- and MCU-domain

Felix Heil

Part Number: AM2434

Hello,

we are using the Industrial Comms SDK 11 and it's included MCU-PLUS SDK.

We are using the M4F for a safe application and the R5F-cluster as well. This also means we use the IPC RPMessage (and thus IpcNotify unerneath). Now the question raised, how do interrupts work?

I could not find any written information but somehow I'm pretty sure I talked with a colleague of TI and the statement was, that if an IPC-packet is send to a core, ALL cores get an interrupt and not only the core which is addressed.
This was a topic once, where we did want to send an interrupt ourselves to a specific core, but TI stated that this is not possible since all cores will get the interrupt.

So how does that behave for the IPC? I can imagine that it happens that inside the R5F-clusters or at least in the MAIN Domain, all cores will get an interrupt if the IPC is used. Does this also affect the MCU-Domain? or is this a separate handling?
This is important, since the M4F is used for a safety-application, it should not be possible to block it via endless interrupts from the MAIN domain.

unfortunately the documentation for IPC in the SDK documentation does not tell much about that. only, that it is SoC specific.

Do you have more info on that?

Best regards

Felix

1 month ago

0 Vaibhav Kumar 1 month ago

TI__Guru 53553 points

Hi,

The assigned expert is out of office, please expect delayed responses.

Regards,

Vaibhav

0 Tushar Thakur 24 days ago

TI__Guru 57308 points

Hi Felix,

Felix Heil said:
I could not find any written information but somehow I'm pretty sure I talked with a colleague of TI and the statement was, that if an IPC-packet is send to a core, ALL cores get an interrupt and not only the core which is addressed.
This was a topic once, where we did want to send an interrupt ourselves to a specific core, but TI stated that this is not possible since all cores will get the interrupt.

The above statement is not true. In the default IPC RPMSG echo example we do send IPC RPMSG to each core. You might be referring to this example.

Or may be you want to say that IPC examples can't be build for a single core, It has to build as System project.

To enable IPC between two or more core or to remove other cores from participating in IPC, please refer [FAQ] PROCESSOR-SDK-AM64X: How to do IPC communication with only two cores ? (say R5FSS0-0 and R5FSS1-1).

Regards,

Tushar

0 Felix Heil 24 days ago in reply to Tushar Thakur

Expert 1265 points

Hey Tushar, thanks for the answer.

I am not sure this answers the question.
I am only talking about the occuring interrupt for the IPC, not for further RPMessage-handling.
My point is: If one core does send an IPC-message, let's say only IpcNotify, will all cores get an interrupt (so will the execution of all cores be interrupted) or only the addressed one?

So I also checked the TRM here we can see in the IPC integration:

It seems that at least a cluster of R5f cores gets an interrupt (or maybe not, because it's distinguished with 0-1 at the end?), but the other cores shouldn't, right?

Checking the interrupt routings for R50_0:

and R50_1:

also tells, that this should be different interrupts.

Well, I think we had a special meeting for that, that's why there wasn't anything written down. We wanted to route a user-interrupts between cores, without IPC and this wasn't possible at the time, because it was stated, that in this case, at least all R5F-cores would receive an interrupt and we would not be able to identifiy its source.

But in the end only one question needs to be answered:

Does the M4F also get interrupted if an IPC-mailbox-message is sent to another R5F-core? Or not at all?
If not, then our "problem" is solved.

Best regards
Felix