• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 152 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSPM0G3519: MSPM0G 6 Phased Clock Outputs?

Fatima Elfasi
Prodigy 210 points

Part Number: MSPM0G3519

Hi team,

I received a question from an engineer at my customer who is developing with the MSPM0G3519. I have included his question below in blue text: 

 

I’m working on a project trying to validate the MSPM0G3519 for a design. I need to take in a 600 kHz clock and output 6 phase shifted versions of that clock. I’ve been running into issues getting them to output & sync correctly.

I tried to manually configure the device without sys config to use TIMA0 C0 as an input to reset the counter & then output different waveforms with C1-4, but I wasn’t able to get this working correctly. I don’t think that will actually be able to do what I need.

I tried to configure sys config to use a GPIO as an input that triggers an event to TIMA0, & TIMA1, but when I have this running & the same configuration set on the 4 PWM channels on TIMA0 I only get an output on one of them, but the complementary outputs work.

I’m not sure if I’m going about this entirely wrong, but it seems like it should be a relatively simple.  I wouldn’t have any trouble doing this with the C2000s I’m used to. Do you have any advice on how to do the 6 phased outputs?

 

Thank you for the support and please let me know if you have any questions.

  • 0
    TI__Expert 7460 points

    HI Fatima,

    I am working on putting together a project attempting to achieve this. I hope to have something completed by EOD tomorrow. Again, sorry for the delay on this.

    Best Regards,
    Brian

  • 0 in reply to Brian Lee
    TI__Expert 7460 points

    Hi Fatima,

    Here is the sample code I created to phase the same clock source 6 times at 600kHz:

    sysctl_hfxt_run_LP_MSPM0G3519_nortos_ticlang.zip

    The following is a screenshot of a Saleae capture from running the attached project:

    The Example uses the following pins in order of synchronization: PA22, PA11, PA1, PA29, PA10, PA0.

    For PA10 and PA11, Jumpers on J12 and J13 need to be changed from XDS to BP.

    For PA0 and PA1, Jumpers are required on J16 and J17 to apply the external Pull-ups. These pins are open drain.

    Is this what they were hoping to achieve?

    Best Regards,
    Brian