Part Number: TMS570LC4357
Hello TI Support,
I’m implementing a PBIST driver for TMS570LC4357 and need a precise clarification about the PBIST ROM Mask Register (ROM[1:0]) interaction with ALGO and RINFOx.
Document: SPNU563A (March 2018), PBIST chapter.
Key register references (SPNU563A Table 9-1):
OVERoffset 0x188 (Section 9.5.5 / Table 9-6)ROMoffset 0x1C0 (Section 9.5.10 / Table 9-14)ALGOoffset 0x1C4 (Section 9.5.11 / Table 9-15)RINFOLoffset 0x1C8 (Section 9.5.12 / Table 9-16)RINFOUoffset 0x1CC (Section 9.5.13 / Table 9-17)DLRoffset 0x164 (Section 9.5.2)
What is clear
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OVER0behavior is explicit (Section 9.5.5 / Table 9-6):OVER0=1: ROM memory mask overridesRINFOL/RINFOU.OVER0=0:RINFOL/RINFOUare used, and the NOTE requires selecting only compatible RAM types and RAM groups valid for all enabled algorithms.
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ROM[1:0]meanings are explicit (Section 9.5.10 / Table 9-14):ROM=0: No information is used from ROM.ROM=1: Only RAM Group information from ROM.ROM=2: Only Algorithm information from ROM.ROM=3: Both Algorithm and RAM Group information from ROM (recommended for application self-test).
The ambiguity (and why Example 9.6.1 triggers it) SPNU563A Section 9.6.1 “Example 1: Configuration of PBIST Controller to Run Self-Test on DCAN1 RAM” programs:
OVER = 0x0(disable RAM override)ALGO = 0x00000004(March13N two-port)RINFOL = 0x00000004,RINFOU = 0x00000000(select DCAN1 group)- then still sets
ROM = 0x3 (Both Algorithm and RAM Group information from ROM ,then why did we set algo and rinfoX ? ) - then starts with
DLR = 0x14
This raises two concrete questions:
Question 1 (directly verifiable): In Example 9.6.1, what would happen if we change only step 9 from ROM=0x3 to ROM=0x0, while keeping:
OVER=0x0ALGO=0x00000004RINFOL=0x00000004,RINFOU=0x00000000DLR=0x14
Would PBIST still execute March13N on DCAN1 as selected by ALGO/RINFOx, or would the run fail / run nothing / behave differently because ROM metadata is not used?
Question 2 (precedence): When ROM includes “Algorithm information from ROM” (ROM=0x2 or ROM=0x3), does PBIST still use the ALGO register as the algorithm enable mask, or does ROM selection override/replace the ALGO selection?
We understand OVER0 only affects RAM-group selection precedence (ROM mask overwrites RINFOx when OVER0=1). The unclear part is the precedence between ROM and ALGO when ROM indicates algorithm info is sourced from ROM.
If there is a recommended configuration pattern to avoid unintended behavior (especially for safety-oriented software), please share it.
Thanks,