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TMS570LC4357: TMS570LC4357 PBIST: clarify precedence of ROM[1:0] vs ALGO (SPNU563A Table 9-14 / 9-15)

Part Number: TMS570LC4357

Hello TI Support,

I’m implementing a PBIST driver for TMS570LC4357 and need a precise clarification about the PBIST ROM Mask Register (ROM[1:0]) interaction with ALGO and RINFOx.

Document: SPNU563A (March 2018), PBIST chapter.

Key register references (SPNU563A Table 9-1):

  • OVER offset 0x188 (Section 9.5.5 / Table 9-6)
  • ROM offset 0x1C0 (Section 9.5.10 / Table 9-14)
  • ALGO offset 0x1C4 (Section 9.5.11 / Table 9-15)
  • RINFOL offset 0x1C8 (Section 9.5.12 / Table 9-16)
  • RINFOU offset 0x1CC (Section 9.5.13 / Table 9-17)
  • DLR offset 0x164 (Section 9.5.2)

What is clear

  1. OVER0 behavior is explicit (Section 9.5.5 / Table 9-6):

    • OVER0=1: ROM memory mask overrides RINFOL/RINFOU.
    • OVER0=0RINFOL/RINFOU are used, and the NOTE requires selecting only compatible RAM types and RAM groups valid for all enabled algorithms.
  2. ROM[1:0] meanings are explicit (Section 9.5.10 / Table 9-14):

    • ROM=0: No information is used from ROM.
    • ROM=1: Only RAM Group information from ROM.
    • ROM=2: Only Algorithm information from ROM.
    • ROM=3: Both Algorithm and RAM Group information from ROM (recommended for application self-test).

The ambiguity (and why Example 9.6.1 triggers it) SPNU563A Section 9.6.1 “Example 1: Configuration of PBIST Controller to Run Self-Test on DCAN1 RAM” programs:

  • OVER = 0x0 (disable RAM override)
  • ALGO = 0x00000004 (March13N two-port)
  • RINFOL = 0x00000004RINFOU = 0x00000000 (select DCAN1 group)
  • then still sets ROM = 0x3 (Both Algorithm and RAM Group information from ROM ,then why did we set algo and rinfoX ? ) 
  • then starts with DLR = 0x14

This raises two concrete questions:

Question 1 (directly verifiable): In Example 9.6.1, what would happen if we change only step 9 from ROM=0x3 to ROM=0x0, while keeping:

  • OVER=0x0
  • ALGO=0x00000004
  • RINFOL=0x00000004RINFOU=0x00000000
  • DLR=0x14

Would PBIST still execute March13N on DCAN1 as selected by ALGO/RINFOx, or would the run fail / run nothing / behave differently because ROM metadata is not used?

Question 2 (precedence): When ROM includes “Algorithm information from ROM” (ROM=0x2 or ROM=0x3), does PBIST still use the ALGO register as the algorithm enable mask, or does ROM selection override/replace the ALGO selection?

We understand OVER0 only affects RAM-group selection precedence (ROM mask overwrites RINFOx when OVER0=1). The unclear part is the precedence between ROM and ALGO when ROM indicates algorithm info is sourced from ROM.

If there is a recommended configuration pattern to avoid unintended behavior (especially for safety-oriented software), please share it.

Thanks,

  • Hi mc,

    Question 1 (directly verifiable): In Example 9.6.1, what would happen if we change only step 9 from ROM=0x3 to ROM=0x0, while keeping:

    If you change only step 9 from ROM=0x3 to ROM=0x0 while keeping all other settings the same:

    The PBIST would NOT execute properly. With ROM=0x0, the controller ignores all ROM-stored information about both algorithms and RAM groups.

    When ROM=0x0:

    • The controller will only use explicitly programmed values from ALGO and RINFOx registers
    • However, it still needs ROM information to properly configure the test for specific RAM groups
    • The PBIST controller requires ROM metadata to properly execute the algorithms against the specified RAM groups

    The example sets ROM=0x3 specifically because the controller needs the ROM-stored configuration data to properly execute the March13N algorithm on the DCAN1 RAM.

    Question 2 (precedence): When ROM includes “Algorithm information from ROM” (ROM=0x2 or ROM=0x3), does PBIST still use the ALGO register as the algorithm enable mask, or does ROM selection override/replace the ALGO selection?

    When ROM includes "Algorithm information from ROM" (ROM=0x2 or ROM=0x3):

    The ALGO register acts as an enable mask that selects from available ROM algorithms, not a replacement.

    • The ALGO register selects which algorithms from ROM will be executed
    • The ROM provides the implementation details of those algorithms
    • Both are required: ALGO selects, ROM provides the algorithm details

    The apparent contradiction in Example 9.6.1 exists because:

    1. First, you select the algorithm via ALGO register (March13N = 0x00000004)
    2. Then, you enable ROM information via ROM=0x3
    3. The controller uses your ALGO selection to determine which ROM-defined algorithm to execute

    --
    Thanks & regards,
    Jagadish.

  • Hi Jagadish,
    
    Thanks for the explanation.
    
    I still see one ambiguity that is important for us from a safety perspective (TMS570LC4357, application PBIST):
    
    1) Is ROM = 0x0 a *supported* and *fully specified* configuration for application code on TMS570LC4357, or should it be considered "not supported / internal only"?
    
       - The TRM (SPNU563A, Table 9-14) describes ROM=0 as "No information is used from ROM".
       - However, from your answer and from Example 9.6.1 behavior, it sounds like ROM=0 cannot be used to run a valid PBIST test because the controller still depends on ROM metadata to interpret ALGO and RINFOx.
    
       Can you please confirm explicitly:
       - On TMS570LC4357, is there any valid PBIST test configuration where ROM=0 is intended to be used by application software?
       - Or should ROM=0 be treated as an unsupported mode (e.g. only for manufacturing / internal test), and thus not used in customer software?
    
    2) For safety-related documentation and reviews, we want to use a clear rule like:
       - "For application PBIST, always set ROM = 0x3. Other ROM values are not to be used."
    
       Is this rule correct and acceptable from TI’s point of view for TMS570LC4357?
    
    3) Finally, could TI please clarify (or confirm) the intended precedence in the TRM:
       - When ROM indicates "algorithm information from ROM" (ROM=2 or 3), ALGO is still the *enable mask* that selects which algorithms to run, and ROM merely defines those algorithms (i.e., ROM does not override ALGO selection). Is this correct?
    
    If possible, it would be very helpful if this could be clarified in an app note or a TRM update/errata, since this affects how we justify our PBIST configuration in safety documentation.
    
    Best regards,
    Mehmet Can
  • Hi Mehmet Can,

    1. Regarding ROM = 0x0 Configuration:

    Explicit confirmation: ROM=0x0 should be treated as not supported for application software on the TMS570LC4357.

    While the TRM technically describes ROM=0 as "No information is used from ROM," this configuration:

    • Is not demonstrated in any application examples
    • Cannot properly execute PBIST tests as the controller requires ROM metadata
    • Is likely reserved for specialized manufacturing or internal test purposes

    The controller architecture fundamentally relies on ROM-based algorithm definitions to properly execute tests, even when ALGO and RINFOx registers are explicitly configured.

    2. Safety Related Rule Confirmation:

    Yes, your proposed rule is correct and aligns with TI's recommendations:

    For application PBIST, always set ROM = 0x3. Other ROM values are not to be used.

    This rule:

    • Matches TI's recommended configuration in Example 9.6.1
    • Ensures proper operation of the PBIST controller

    3. Precedence Confirmation:

    Correct understanding: When ROM=2 or ROM=3 (algorithm information from ROM):

    • ALGO acts as an enable mask that selects which algorithms to run
    • ROM defines the algorithms but does not override the ALGO selection
    • Both registers work together: ROM provides the algorithm definitions, ALGO enables specific algorithms

    --
    Thanks & regards,
    Jagadish.