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TM4C1292NCPDT: PLL rising falling timing adjustment

Ryuuichi machida
Guru 13090 points

Part Number: TM4C1292NCPDT

Hi,

I would like you to consult about below.

*One of my customer had problem related to signal reflection for divsclk.

Customer set low drive strength to care overshoot, however, high frequency components interfare rising and falling edge of this clk.
As a result, customer observed distorition (non linearity components) on rising and falling edge.

Customer solved this by changing higher drive strengh of to divsclk (instread of distortion, customer show overshoot) , however customer have following question to PLL of TM4C.

* Datasheet "5.2.5.5 PLL " show how desired clock source is genenrated, however this shows only frequency factor. Is there any advice how we should control slope of rising / falling edge of output of PLL ?
(ex, can control related to VCO factor such as reactance to adjust loop filter..)
 
Best Regards,

  • 0
    TI__Mastermind 23715 points

    Hi 

    In the TM4C1292NCPDT, there are no direct registers to adjust the "rising and falling timing" (slew rate) of the internal PLL itself. Instead, timing adjustments usually refer to output signal integrity for the clock signals derived from the PLL, or managing jitter through PLL configuration

    To optimize the PLL's stability and minimize timing variations:
    1, VCO Frequency: The PLL's VCO should be set to either 320 MHz or 480 MHz.
    2, Integer Multiplier (MINT): Jitter is minimized when the fractional part (MFRAC) in the RSCLKCFG Register (Run and Sleep Mode
    Configuration Registe) is zero.
    3, Wait for Lock: Ensure the PLL has fully locked (checking the PLLSTAT register) before switching the system clock to the PLL source to avoid unstable timing during the transition

    Thanks

  • 0 in reply to Xiaodong LI
    Guru 13090 points

    Hi,

    Thank you for your reply.
    >Instead, timing adjustments usually refer to output signal integrity for the clock signals derived from the PLL
    Is there any application note which have advice for above point ?

    Best Regards,