• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 30 subscribers
  • Views 982 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS3137 SPICLK,VCLK

suresh B91852
Intellectual 300 points
Other Parts Discussed in Thread: TMS570LS3137, HALCOGEN

Hi,

 

Can any one let me know the frequency of VCLK.

I am trying to Interface TMS570LS3137 with Altera CPLD EPM570F256I5-5.

Where i will be using the MibSPI1 for this interface to access with processor.

I will be collecting the Data from resolver to digital converter RD19240  (where parallel data is converted into serial) andf then through SPI interface from CPLD to Processor .

For your refrence i had attached the Logic which im going to implement in the CPLD.

Kindly provide the VCLK frequecny to calculate the timing analysis for SPI interface.

Else plese provide the timing analysis of MibSPI interface.

 

Regards

Suresh.B

  • 0
    TI__Mastermind 49120 points

    Hi Suresh,

    The VCLK clock domain frequency is divided down from the HCLK frequency. The max supported VCLK frequency is 100MHz. This is specified in table 3-1 on page 43 of SPNS162 (datasheet for TMS570LS3137).

    The maximum supported SPICLK frequency is 25MHz. You can choose the appropriate divider in the MibSPI module format control registers based on the VCLK frequency you choose.

    Regards, Sunil 

  • 0 in reply to Sunil Oak
    Intellectual 300 points

    Hi,

    I am providing 16MHz external clock for the processor, so kindly let me know the frequencies and following timing details.

    I am using the processor in master mode configuration.

     if i want to retain the default value without changing C2TDELAY register what could be the  tf(SPICS), tr(SPC).

    Spi timing detailed diagram for 16Mhz clock and if i want to change  C2TDELAY register value kindly provide me an example to do so.

    Regards

    Suresh

     

  • 0 in reply to Sunil Oak
    Intellectual 300 points

     

    Hi,

    I am providing 16MHz external clock for the processor, so kindly let me know the frequencies and following timing details.

    I am using the processor in master mode configuration.

     if i want to retain the default value without changing C2TDELAY register what could be the  tf(SPICS), tr(SPC).

    Spi timing detailed diagram for 16Mhz clock and if i want to change  C2TDELAY register value kindly provide me an example to do so.

     

    And how to decide timings on  rise time and fall time.

    Switching Characteristics for Output Timings versus Load Capacitance (CL)

  • 0 in reply to suresh B91852
    TI__Mastermind 49120 points

    Hello,

    The SPI CLK frequency is generated by dividing down the peripheral bus clock domain VCLK. VCLK is in turn generated by dividing down the system bus clock HCLK. The system module control register GHVSRC is used to select the clock source for the GCLK (CPU clock), HCLK and VCLK domains.

    The C2TDELAY is programmable in the MibSPIx and SPIx module control registers. I suggest that you install the HALCoGen utility that allows you to configure these timings for the SPIx and MibSPIx modules. This utility will then generate an initialization function with the settings you pick.

    The rise and fall times of output signals are dependent on the capacitive loads that the signal has to drive. The output buffer timings table shows the rise and fall times for some specific loads on each output buffer type. The type of the output buffer used for each MibSPI or SPI signal is described in the "Output buffer drive strengths" section of the datasheet.

    Regards, Sunil