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TMS570LS1227: TMS570 EMIF Read vs. Write Timings

Will Neff
Prodigy 60 points

Part Number: TMS570LS1227

Hi,

I am experiencing something that I don't believe is described in the device datasheet or Technical Reference Manual.  My EMIF reads are about half the speed of my EMIF writes with the same number of wait states applied to both read and write.

My configuration:
EMIF mode: Asynchronous Normal Mode
EMIF bus width: 16-bits
EMIF clock: 180MHz
Read/Write Setup Wait States Register: 0
Read/Write Strobe Wait States Register: 24
Read/Write Hold Wait States Register: 0

I can run this code with everything exactly the same except commenting out the read vs. write directions and as mentioned, the read direction takes about twice as long.
image.png

EMIF Read Capture ~3us for 9 16-bit values:
image.png

EMIF Write Capture ~1.5us for 9 16-bit values:
image.png

It seems like the problem area is the amount of time that the CS line remains high.  The rest of the timings look to match between read and write.

Any ideas?

Thank you,
Will

  • +1
    TI__Guru* 77096 points

    Hi Will,

    Some potential possibilities:

    1. Read vs Write Pipeline Differences: The TMS570 core might need to wait for read data to return before proceeding with the next instruction, while write operations can be posted (the CPU continues execution before the write completes).

    2. Memory Barrier Effects: When reading from external memory, the processor typically has to wait for the data to arrive before continuing. Writes can often be buffered.

    3. CS (Chip Select) Timing: Your observation about CS line timing is significant. The chip select may need to remain active longer during reads to ensure data is properly sampled.

    4. Wait State Implementation: Even though you've configured identical wait states for both operations, the hardware might implement them differently for reads vs writes.

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 60 points

    Hi Jagadish,

    Thanks for your reply.  The capture I provided was taken with the EMIF configured for its maximum clock speed of 180MHz.  I took some more captures running at 90MHz and the timings between reads vs. writes were much closer together.

    This makes me suspect that one or more of your listed possibilities is occurring.  It is not an issue for us that reads may take a little longer, I just wanted to make sure this wasn't totally unexpected behavior.

    Thanks,
    Will