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AM6442: AM6442 MDIO Mode and Ethernet Architecture

Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

Hello,

I am working with AM6442, SDK-->11.2.0.24 and SysConfig-->1.25.0 Ethernet peripherals (CPSW and ICSSG) and would like to gain a deeper understanding of the MDIO configuration operating modes available in SysConfig, specifically what each mode means and which parts of the system behavior they affect. I could not find sufficiently detailed explanations in the SDK documentation regarding how these modes differ internally, both at driver and hardware levels.

Under SysConfig → MDIO Config → Operating Mode, the following modes are available:

  • MDIO_MODE_NORMAL

  • MDIO_MODE_MANUAL

  • MDIO_MODE_STATE_CHANGE_MON

My current understanding is as follows:

  • MDIO_MODE_NORMAL: The driver fully manages the PHY via MDIO, including reset, auto-negotiation, speed/duplex configuration, and link status monitoring.

  • MDIO_MODE_MANUAL: MDC and MDIO are enabled, but automatic PHY management is disabled, and all PHY register accesses and initialization sequences are handled by the application.

  • MDIO_MODE_STATE_CHANGE_MON: MDIO register access is disabled, and this mode is intended only to monitor PHY link state changes.

However, I would like to better understand what exactly changes internally when switching between these modes — specifically which hardware signals, driver features, or firmware mechanisms are enabled or disabled in each case.

In particular, when MDIO_MODE_STATE_CHANGE_MON is selected and “Enable MDIO MDC Config” is disabled, SysConfig removes the MDC and MDIO pins from the pinmux configuration. While this behavior makes sense electrically, the following points are not entirely clear to me:

  1. When MDC and MDIO are disabled, how does the CPSW / ICSSG Ethernet subsystem obtain PHY link up/down status, speed, and duplex information?

    • Are these parameters derived purely from the MAC–PHY interface signals (such as RGMII / SGMII / MII),

    • or is there a different monitoring or state-machine mechanism implemented inside the CPSW / ICSSG firmware or driver?

  2. In MDIO_MODE_STATE_CHANGE_MON, is it assumed that the PHY is:

    • Already configured via strap pins, and/or

    • Managed by another MAC instance that owns the MDIO master role?
      In this mode, can the MAC port be considered a purely passive observer with respect to PHY management?

  3. Is it technically correct to state that MDIO is strictly a management bus, and that Ethernet data transmission and reception (TX/RX frame traffic) are completely independent of MDIO, which would explain why disabling MDC/MDIO does not prevent normal Ethernet data operation?

In addition, I would also like to understand the differences between Switch mode and Dual MAC mode for CPSW and ICSSG Ethernet. Specifically:

  • What are the key differences between these modes at the hardware, firmware, and driver levels?

  • How do MAC addressing, MDIO usage, NETIF structure, and inter-port data forwarding differ between Switch mode and Dual MAC mode?

  • For which use cases is Switch mode recommended, and for which scenarios is Dual MAC mode the intended configuration?

I was not able to find sufficiently detailed explanations for these topics in the SDK documentation, and I would like to ensure that my understanding of the intended CPSW / ICSSG Ethernet architecture and configuration model aligns with TI’s design.

Thank you in advance for your clarification.

  • Hello Berlam,

    Thank you for your query !

    Please allow me some time to internally check the TI available documentation and discuss.

    Please expect my response early next week.

    Thanks for your patience !

    Kind Regards

    Anastas Yordanov

  • Hello Anastas,

    I'm looking forward to your reply with great impatience. Thank you very much in advance.

  • Hi Berlam,

    Sorry for the time gap in the expected response !

    I haven't forgotten about your request but had to deal with numerous tasks recently.

    Please expect my reply later today (COB).

    Thanks

    Best Regards

    Anastas Yordanov

  • Hello Berlam,

    In addition, I would also like to understand the differences between Switch mode and Dual MAC mode for CPSW and ICSSG Ethernet. Specifically:

    • What are the key differences between these modes at the hardware, firmware, and driver levels?

    • How do MAC addressing, MDIO usage, NETIF structure, and inter-port data forwarding differ between Switch mode and Dual MAC mode?

    • For which use cases is Switch mode recommended, and for which scenarios is Dual MAC mode the intended configuration?

    For the first two questions I need to discuss/check internally with our software dev team. You mentioned you couldn't find sufficiently detailed explanations for these in SDK documentation, can you share the specific resources/link you are looking at?

    For the third question,

    Switch Mode:

    Switch mode is useful if you are planning on using the Ethernet ports on TI AM6x processors as a switch, such as forwarding packets from one port directly to the other port. Typically used when multiple ports of the AM64x device are connected to the same subnet. 

    To configure for switch mode with CPSW in Linux, you can use the steps provided in https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW3g.html#multi-port-switch-mode 

    To configure for switch mode with ICSSG in Linux, you can use the steps provided in https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/latest/exports/docs/linux/Foundational_Components/PRU-ICSS/Linux_Drivers/PRU_ICSSG_Ethernet_Switch.html 

    Dual MAC Mode:

    This mode is commonly used when you require complete separation of the ports on TI AM6x processors (e.g. traffic from eth0 should be isolated from traffic from the other ports). In this mode, the ports should each be on a completely different subnet.

    By default for both ICSSG and CPSW ports, this is the mode that the interfaces get bring up as when on Linux.

    -Daolin

  • Hi Daolin,

    Thank you very much for supporting the thread !

    Best Regards,

    Anastas

  • Following up on Daolin's response, one of the benefits of having a CPSW hardware switch or a PRU Ethernet HW switch is that the peripheral can check an Ethernet packet's information to see if the packet was intended for the AM64x, and if not, then it can push the packet out the other side of the switch without sending any data back to the controlling processor core. This is much faster than an implementation where the Linux OS or the R5F core has to receive the Ethernet packet, and then decide whether to forward the packet out the other side of the switch, or to process the packet within the AM64x.

    Since you are using SysConfig to configure the Ethernet interface, I assume you are controlling the Ethernet interface from an MCU+ core. I am sending your thread over to a member of our MCU+ team to comment on the other questions.

    Regards,

    Nick