Part Number: MSPM0G3507
Dear TI Forum,
I am referring to the document: Functional Safety Manual for MSPM0G3x0x-Q1(SFFS624B – MARCH 2024 – REVISED AUGUST 2025), and to Section 5.5 CPU.
There the following is stated "ARMv6-M thumb instruction set (little endian) with single-cycle 32×32 multiply instruction".
My question is: why is the single cycle multiplication is being highlighted here? Is this referring simply to the MULS <Rdm>,<Rn>,<Rdm> (encoding: 0 1 0 0 0 0 1 1 0 Rn Rdm) instruction from the ARM-v6M ISA Manual or is this like a custom addition from TI to the standard ISA?
Thank you in advance for your help!
