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AM2431: Unexpected LPDDR4 Register Write Behavior on AM2431

Kanno Itsuki
Prodigy 60 points

Part Number: AM2431
Other Parts Discussed in Thread: SYSCONFIG

We are using AM2431 with LPDDR4, and we observe several unexpected behaviors when writing to DDRSS registers.
We also confirm that the DDR configuration file is generated using the latest SysConfig tool.

We would like to ask:
Is this expected behavior or a problem?
If it is expected, under what conditions does the hardware behave this way?

Below are the phenomena we see:

1. Writing to DDR16SS0_PI_0(0x0F30A000) seems to alter other PI registers
Using:
CPS_REG_WRITE(LPDDR4_AddOffset(&(ctlRegBase->DENALI_PI_0), regOffset), regValue)

some unrelated registers (e.g., DDR16SS0_PI_53) receive unexpected values like 0xFF, which are not defined in the header file.

2. Written value differs from actual register value
Using:
CPS_REG_WRITE(LPDDR4_AddOffset(&(ctlRegBase->DENALI_PI_0), regOffset), regValue

Example (e.g., DDR16SS0_PI_145 (0x0F30A244)):

Expected: 0x00010003
Actual readback: 0x40010003

A bit is unexpectedly set after the write.

3. Only PHY_REG area 0x0F30D000 to 0x0F30D0AC appears shifted by one register
After writing DDR16SS0_PHY_1360, the PHY_REG(0x0F30D000 to 0x0F30D0AC) block appears offset by one.

Our question

Are these symptoms normal for DDRSS/PHY initialization?
If yes, in what situations can:

register contents temporarily change,
neighboring registers be affected,
or PHY register addressing appear shifted?

If this is not expected, we would appreciate guidance.
Thank you for your support.
KANNO, Itsuki

  • 0
    TI__Guru* 90765 points

    This is expected behavior.  Some registers initiate hardware sequences which will change values in other registers (for example, status registers).  There are quite a few interdependencies among the register set, too many to detail.  Note we don't expect customer to manually set registers as you are doing.  You should use the DDR Register Configuration Tool at dev.ti.com/sysconfig to configure all of the registers in the DDR Subsystem.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 60 points

    James,

    Thank you for the clarification.
    I understand that the behavior I observed is expected due to the interdependencies among the registers, and that manual register configuration is not assumed.

    Based on your guidance, I will rely on the DDR Register Configuration Tool in SysConfig for setting up the DDR subsystem.

    Regards,
    KANNO, Itsuki