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AM2612-Q1: Data address changes in map file when using 2 core

Alpha Han
Expert 3790 points

Part Number: AM2612-Q1
Other Parts Discussed in Thread: AM2612, SYSCONFIG

My project used two cores (R5FSS0-0 & R5FSS0-1) of AM2612.  One variable(named g_stShmRData) address in map file (r5fss0-0.Release.map) will be modified , after core R5FSS0-1 compile completed. The variable g_stShmRData is the shared memory between two cores.

 

Before be modified (only compile core R5FSS0-0):

The variable g_stShmRData is 0x70170000.

After be modified (core  R5FSS0-0 compiled complete):

The variable g_stShmRData is  0x40. This address is located in TCMA. And the length of TCMA is equal to the length of variable g_stShmRData.

 

Below are my questions:

Question 1: Is this phenomenon reasonable? If not, how should it be investigated and corrected?

Question 2: Given the current syscfg version: sysconfig_1.22.0 and SDK version: mcu_plus_sdk_am261x_10_00_01_10, configuring the Page attribute of the memory region (used to modify the linker file) is not supported. Are there any alternative methods ?

  • 0
    TI__Expert 6205 points

    Hi Alpha Han,

    Let me check this from my side and get back to you.

    Regards,

    Aswin

  • 0
    TI__Expert 6205 points

    Hello Alpha Han,

    Alpha Han said:
    Question 1: Is this phenomenon reasonable? If not, how should it be investigated and corrected?

    This is not an expected phenomenon. I tried to replicate this issue using a shared variable in the ipc_notify_echo example and could not replicate this issue. I used the same SDK and sysconfig version as mentioned. Is it possible for the customer to share a project where this issue is occurring.

    Alpha Han said:
    Question 2: Given the current syscfg version: sysconfig_1.22.0 and SDK version: mcu_plus_sdk_am261x_10_00_01_10, configuring the Page attribute of the memory region (used to modify the linker file) is not supported. Are there any alternative methods ?

    Is this about configuring R/W/X permissions for memory regions in linker script. If so, this can be done via sysconfig. Please see the attributes section of a memory region.

    Regards,

    Aswin

  • 0 in reply to Aswin Sankar
    TI__Expert 3175 points

    Hi Aswin,

    I think customer want to define a shared variable between core0 and core1 in OCRAM,

    can they use below definition:

    volatile int shared_var1 __attribute__((location(0x70050000))) = 0;
    volatile int shared_var2 __attribute__((location(0x70060000))) = 0;
    BRs
    Shuqing
  • 0 in reply to Shuqing Zhou
    TI__Expert 6205 points

    Hi Shuquing, 

    I tried out this method. 
    Please see my map files screen shots. On left it is core0-0 and on right it is core0-1.

    In my linker script, I have defined a memory region. This is done for both linker files.

    I have also attached the zip file of my project. Please see the file ipc_notify_echo.c in both the projects.

    ipc_notify_echo_am261x-lp.zip

    Regards,

    Aswin

  • 0 in reply to Aswin Sankar
    TI__Expert 3175 points

    Hi Aswin,

    We find if we disable the Optishare, the result is as expected(core0 and core1 can use the shared variable that we defined)

    but if we enable it, the result is not expected(shared variable between core1 and core0 isn't has the same address)

    And we check the Optishare concept: AM261x MCU+ SDK: Optishare

    But maybe we have a wrong understanding this, from the AM261x MCU+ SDK: Optishare, my understanding is that if we would realize the shared variable we should enable Optishare(this is not same as the test result), could you help to explain it?

    BRs

    Shuqing

  • 0 in reply to Shuqing Zhou
    TI__Expert 6205 points

    Hi Shuqing,

    Shuqing Zhou said:
    my understanding is that if we would realize the shared variable we should enable Optishare(this is not same as the test result), could you help to explain it?

    For sharing a variable there is no needs to enable optishare. 

    The scenario where optishare would be used is as below,

    Suppose core 0 is using some libraries/functions. And there is core 1 who is also using the same libraries/functions. Without optishare, these libraries would be placed in the memory twice because both the cores need it. This causes memory wastage due to redundancy. But if optishare is enabled, then this library would be placed only once is memory and both cores would access the same code.

    This idea is shown in this picture.

    Thanks & Regards,

    Aswin