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AM2634: RTI Timers are getting stooped in Debug Mode

Gopala Lakshmana Swamy Tummala
Prodigy 10 points

Part Number: AM2634

Hi, I need help understanding why my timers stop running while debugging. We are using three different hardware timers in our code (500 µs, 1 ms, and 256 ms). During debugging, one of the timers eventually stops, and its interrupt flag is not getting cleared. We tried changing the stall mode (both ON and OFF), and it is currently set to ON, but the issue persists.

Can someone help me figure out why this is happening? and how to resolve

 

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  • 0
    TI__Mastermind 19202 points

    Hi,

    1. Can you please share the RTI register dump for all three RTI instances being used?

    2. May I know how do you confirm that the specific RTI2 is stopping.

    3. Can you share your example.syscfg file as well.

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    Prodigy 10 points

    Hi,

    i'm providing the related information.

    ->

    When the code functionality stops which is called in rti callback, I set a breakpoint to check whether the ISR is still being triggered or not. I also verified this by toggling three different pins and observing them on an oscilloscope. The issue doesn’t consistently occur on a specific timer like RTI2—instead, the behaviour is apply to other timers. Sometimes RTI1 and RTI2 stop, and other times a different combination of timers stops.

    ->

    static void Drivers_rtiOpen(void)

    {
    HwiP_Params rtiHwiParams;
    int32_t status;
    uint32_t baseAddr;
    uint64_t timeInNsec;
    uint32_t cntrPrescaler;
    uint32_t compPrescaler;

    baseAddr = CONFIG_RTI1_BASE_ADDR;

    /* Configure RTI input clock source */
    SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MAIN, MSS_RCM_PARTITION0);
    *(volatile uint32_t*)AddrTranslateP_getLocalAddr(CONFIG_RTI1_CLOCK_SRC_MUX_ADDR) = CONFIG_RTI1_CLOCK_SRC_WUCPUCLK;
    SOC_controlModuleLockMMR(SOC_DOMAIN_ID_MAIN, MSS_RCM_PARTITION0);

    /* Enable/Disable Continue on Suspend */
    RTIG_setStallMode(baseAddr, RTI_GC_STALL_MODE_ON);

    /* Configure Counter block 0 */
    cntrPrescaler = (CONFIG_RTI1_INPUT_CLK_HZ/CONFIG_RTI1_CNTR0_OUTPUT_CLK_HZ) - 1;
    RTI_counterConfigure(baseAddr, RTI_TMR_CNT_BLK_INDEX_0, RTI_TMR_CLK_SRC_COUNTER, RTI_TMR_NTU_0, cntrPrescaler);
    RTI_captureConfig(baseAddr, RTI_TMR_CNT_BLK_INDEX_0, RTI_TMR_CAPTURE_EVT_0);


    /* Configure Compare event 0 */
    timeInNsec = CONFIG_RTI1_NSEC_PER_TICK_COMP0;
    if(timeInNsec == 0)
    {
    timeInNsec = CONFIG_RTI1_USEC_PER_TICK_COMP0 * 1000U;
    }
    compPrescaler = (timeInNsec*CONFIG_RTI1_COMP0_INPUT_CLK_HZ)/1000000000;

    RTI_compareEventConfig(baseAddr, RTI_TMR_CMP_BLK_INDEX_0, CONFIG_RTI1_COMP0_SRC, compPrescaler, compPrescaler);
    RTI_intStatusClear(baseAddr, RTI_TMR_INT_INT0_FLAG);
    HwiP_Params_init(&rtiHwiParams);
    rtiHwiParams.intNum = CONFIG_RTI1_INT_NUM_EVENT0;
    rtiHwiParams.callback = RTI1_event0Isr_1mSec;
    rtiHwiParams.isPulse = 0; // level Edge but we tried with pulse edge but same result
    rtiHwiParams.priority = 13;
    status = HwiP_construct(&gRtiEvent0HwiObj[CONFIG_RTI1], &rtiHwiParams);
    DebugP_assertNoLog(status==SystemP_SUCCESS);

    RTI_intEnable(baseAddr, RTI_TMR_INT_INT0_FLAG);

    RTI_intDisable(baseAddr, RTI_TMR_INT_DMA0_FLAG);


    baseAddr = CONFIG_RTI2_BASE_ADDR;

    /* Configure RTI input clock source */
    SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MAIN, MSS_RCM_PARTITION0);
    *(volatile uint32_t*)AddrTranslateP_getLocalAddr(CONFIG_RTI2_CLOCK_SRC_MUX_ADDR) = CONFIG_RTI2_CLOCK_SRC_WUCPUCLK;
    SOC_controlModuleLockMMR(SOC_DOMAIN_ID_MAIN, MSS_RCM_PARTITION0);

    /* Enable/Disable Continue on Suspend */
    RTIG_setStallMode(baseAddr, RTI_GC_STALL_MODE_ON);

    /* Configure Counter block 0 */
    cntrPrescaler = (CONFIG_RTI2_INPUT_CLK_HZ/CONFIG_RTI2_CNTR0_OUTPUT_CLK_HZ) - 1;
    RTI_counterConfigure(baseAddr, RTI_TMR_CNT_BLK_INDEX_0, RTI_TMR_CLK_SRC_COUNTER, RTI_TMR_NTU_0, cntrPrescaler);
    RTI_captureConfig(baseAddr, RTI_TMR_CNT_BLK_INDEX_0, RTI_TMR_CAPTURE_EVT_0);


    /* Configure Compare event 0 */
    timeInNsec = CONFIG_RTI2_NSEC_PER_TICK_COMP0;
    if(timeInNsec == 0)
    {
    timeInNsec = CONFIG_RTI2_USEC_PER_TICK_COMP0 * 1000U;
    }
    compPrescaler = (timeInNsec*CONFIG_RTI2_COMP0_INPUT_CLK_HZ)/1000000000;

    RTI_compareEventConfig(baseAddr, RTI_TMR_CMP_BLK_INDEX_0, CONFIG_RTI2_COMP0_SRC, compPrescaler, compPrescaler);
    RTI_intStatusClear(baseAddr, RTI_TMR_INT_INT0_FLAG);
    HwiP_Params_init(&rtiHwiParams);
    rtiHwiParams.intNum = CONFIG_RTI2_INT_NUM_EVENT0;
    rtiHwiParams.callback = RTI2_event0Isr_500uSec;
    rtiHwiParams.isPulse = 0;
    rtiHwiParams.priority = 14;
    status = HwiP_construct(&gRtiEvent0HwiObj[CONFIG_RTI2], &rtiHwiParams);
    DebugP_assertNoLog(status==SystemP_SUCCESS);

    RTI_intEnable(baseAddr, RTI_TMR_INT_INT0_FLAG);

    RTI_intDisable(baseAddr, RTI_TMR_INT_DMA0_FLAG);

    baseAddr = CONFIG_RTI3_BASE_ADDR;

    /* Configure RTI input clock source */
    SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MAIN, MSS_RCM_PARTITION0);
    *(volatile uint32_t*)AddrTranslateP_getLocalAddr(CONFIG_RTI3_CLOCK_SRC_MUX_ADDR) = CONFIG_RTI3_CLOCK_SRC_WUCPUCLK;
    SOC_controlModuleLockMMR(SOC_DOMAIN_ID_MAIN, MSS_RCM_PARTITION0);

    /* Enable/Disable Continue on Suspend */
    RTIG_setStallMode(baseAddr, RTI_GC_STALL_MODE_ON);

    /* Configure Counter block 0 */
    cntrPrescaler = (CONFIG_RTI3_INPUT_CLK_HZ/CONFIG_RTI3_CNTR0_OUTPUT_CLK_HZ) - 1;
    RTI_counterConfigure(baseAddr, RTI_TMR_CNT_BLK_INDEX_0, RTI_TMR_CLK_SRC_COUNTER, RTI_TMR_NTU_0, cntrPrescaler);
    RTI_captureConfig(baseAddr, RTI_TMR_CNT_BLK_INDEX_0, RTI_TMR_CAPTURE_EVT_0);


    /* Configure Compare event 0 */
    timeInNsec = CONFIG_RTI3_NSEC_PER_TICK_COMP0;
    if(timeInNsec == 0)
    {
    timeInNsec = CONFIG_RTI3_USEC_PER_TICK_COMP0 * 1000U;
    }
    compPrescaler = (timeInNsec*CONFIG_RTI3_COMP0_INPUT_CLK_HZ)/1000000000;

    RTI_compareEventConfig(baseAddr, RTI_TMR_CMP_BLK_INDEX_0, CONFIG_RTI3_COMP0_SRC, compPrescaler, compPrescaler);
    RTI_intStatusClear(baseAddr, RTI_TMR_INT_INT0_FLAG);
    HwiP_Params_init(&rtiHwiParams);
    rtiHwiParams.intNum = CONFIG_RTI3_INT_NUM_EVENT0;
    rtiHwiParams.callback = RTI3_event0Isr_256mSec;
    rtiHwiParams.isPulse = 0;
    rtiHwiParams.priority = 15;
    status = HwiP_construct(&gRtiEvent0HwiObj[CONFIG_RTI3], &rtiHwiParams);
    DebugP_assertNoLog(status==SystemP_SUCCESS);

    RTI_intEnable(baseAddr, RTI_TMR_INT_INT0_FLAG);

    RTI_intDisable(baseAddr, RTI_TMR_INT_DMA0_FLAG);


    }

    the below images contains state of INTflag when my rti stops, here rti1 and rti2 gets stopped.

    Regards,

    Gopala Lakshmana Swamy

  • 0 in reply to Gopala Lakshmana Swamy Tummala
    TI__Mastermind 19202 points

    Hi,

    Let me review and get back.

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    TI__Mastermind 19202 points

    HI,

    A few more questions:

    1. How long is your ISR logic? Generally huge ISR logics can cause delayed interrupt flag clearing and cause timing issues.

    2. Do you set breakpoints in your ISR? IF yes, this is expected,

    3. Can you verify each ISR calls the RTI_intStatusClear() flag.

    4. Can you confirm how many compare and counter events have you configured (i see 3 interrupts) and if you are clearing the interrupts for all of them.

    I believe unconfigured compare blocks 1, 2, 3 are generating spurious interrupts that never get cleared, causing interrupt controller lockup. Clear and disable all compare blocks at initialization, then only enable the one you're using.

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    Prodigy 10 points

    Hi,

    1. my isr contains only led blinking.

    2. if led blinking is stopped, then i'm setting breakpoint and verifying.

    3.yes, all 3 ISR calls  RTI_intStatusClear() inside ISR API.

    4.i've configured one compare and one counter events, clearing interrupt inside ISR API using HwiP_clearInt(). and meanwhile i will check by clearing unconfigured compare blocks

  • 0 in reply to Gopala Lakshmana Swamy Tummala
    TI__Mastermind 19202 points

    Can you please share your ISR code?

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    Prodigy 10 points

    HI, please find isr below.

    Regards,

    Gopala Lakshmana Swamy

  • 0 in reply to Gopala Lakshmana Swamy Tummala
    TI__Mastermind 19202 points

    Hi,

    I believe the issue is that we are only clearing INT0, not all flags, Try to clear all the possible flags instead of just INT0.

    Regards,
    Shaunak