AM263P4: Code Execution Takes longer on AM263P4 Compared to AM2634

Glad that you found the issue. However, please note the following present in the Device TRM (AM263Px Sitara Microcontrollers Technical Reference Manual (Rev. D) section 3.2) with respect to OCSRAM banks access latencies in AM263P:

The placement of 6 L2OCRAM Banks across the 3 interconnects (R5SS0 VBUSM, R5SS1 VBUSM and VBUSM CORE Interconnect) has been done such that cores in a cluster can have faster access (lesser latency) to the banks closer to that particular cluster. In other words, R5SS0_Core0 and R5SS0_Core1 cores will have faster access latency to its near L2OCSRAM banks (BANK0 and BANK1) placed on R5SS0 VBUSM interconnect. Similarly, R5SS1_Core0 and R5SS1_Core1 cores will have faster access latency to its near L2OCSRAM banks (BANK2 and BANK3) placed on R5SS1 VBUSM interconnect. All the 4 cores, will have the same but slower access latency to the common L2OCSRAM banks (BANK4 and BANK5) as compared to their near banks. Furthermore, all the 4 cores will have slower access latency to their far L2OCSRAM banks (BANK2 and BANK3 for cluster R5SS0 and BANK0 and BANK1 for cluster R5SS1) as compared to common banks. To summarize, for particular cores in a cluster, below is the L2OCRAM Bank access latency comparison: Access latency of near banks < Access latency of common banks < Access latency of far banks