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AM2434: ADC HW-enabled Step / CTRLMMR_ADC0_CTRL Register

Christian Dev
Prodigy 30 points

Part Number: AM2434

Hello E2E-Community,

i got a question regarding the ADC0 of the Sitara AM243x. A look in the technical reference manual shows that each step can operate in SW or HW enabled mode. This is also shown in the register description of  ADC_STEPCONFIG_j Register (Offset = 64h + formula). Here the 1-0 set either set SW-enabled single-shot / continous, or HW-enabled single-shot / continous mode. However out of the provided ADC examples only the "adc_singleshot" is can be used out-of-the-box. The other examples do not provide a CCS project as far as I can see. Furthermore I noticed:

  • The "adc_singleshot" example uses the "v0" implementation of the ADC driver only defines two modes -> "ADC_OPERATION_MODE_SINGLE_SHOT" and "ADC_OPERATION_MODE_CONTINUOUS" which are SW enabled e.g. "ADC_OPERATION_MODE_SINGLE_SHOT" is "ADC_STEPCONFIG_MODE_SW_EN_ONESHOT" from "hw_adc.h". HW-enabled modes are not defined in the "v0" driver.
  • The e.g. "adc_soc_ecap" example which does not provide a CCS project seems to use the "v2" implementation of the ADC driver. However using / including the "adc.h" of the "v2" in a blank projekt for the AM243x leads to several errors.
  • Because of that I tried to manually enable / configure HW-enabled Steps manually using the Registers. The figure "ADC0 Integration" in Section 12.1.1.3 shows that the register CTRLMMR_ADC0_CTRL[4-0] TRIG_SEL must be used. During further research the following post caught my attention: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1467859/lp-am243-triggering-adc-with-periodic-timer-trigger-output. In this post Swargam Anil posted a picture of this register in section 5.1.1.5.72. The post is from Jan/2025 and shows that "AM64x / AM243x Silicon Revision 1.0" is used. However I cannot find this section or the CTRLMMR_ADC0_CTRL description in the current technical reference manual. Am I missing something?

It would be helpful to know where the register description for CTRLMMR_ADC0_CTRL is located in the current version of the technical reference manual, so that I can configure the HW-enabled steps manually. Maybe there is a solution to either include the "v2" or extend the "v0" so that I can use HW-enabled steps in a AM243x. Maybe it is also possible to provide a small example.

Best regards,

chr

 

  • 0
    TI__Mastermind 21535 points

    Hi,

    I am looking into this, please expect an update in 1-2 days.

    Best Regards,

    Meet.

  • 0 in reply to Meet Thakar
    TI__Mastermind 21535 points

    Hi Christian,

    Christian Dev said:
    The e.g. "adc_soc_ecap" example which does not provide a CCS project seems to use the "v2" implementation of the ADC driver. However using / including the "adc.h" of the "v2" in a blank projekt for the AM243x leads to several errors.

    The v2 files are not supported for am243 device and should not be used, similarly adc_soc_example is also not supported for am243 MCU+SDK.

    Christian Dev said:
    It would be helpful to know where the register description for CTRLMMR_ADC0_CTRL is located in the current version of the technical reference manual

    You can find it at TRM section 5.1.1.5.72 CTRLMMR_ADC0_CTRL Register:

    Christian Dev said:
    Maybe it is also possible to provide a small example.

    We don't have the example available for this, but you can configure this by making a few changes like, selecting the trigger by modifying the CTRLMMR register and changing the adc mode to Hardware Singleshot from Software singleshot, we already have macros defined for HW modes in hw_adc.h:

    https://github.com/TexasInstruments/mcupsdk-core/blob/next/source/drivers/adc/v0/hw_adc.h#L839 

    You can change the adc mode by changing the following: 

    https://github.com/TexasInstruments/mcupsdk-core/blob/next/examples/drivers/adc/adc_singleshot/adc_singleshot.c#L177 

    Best Regards,

    Meet.

  • 0 in reply to Meet Thakar
    Prodigy 30 points

    Hello Meet,

    thank you for your reply. Your answer helps me take a step forward in knowing that "v2" cannot be used for the AM243x. Thank you also for the register excerpt, but that is where my orginal question comes in. I cannot find Table 5-192 in the current revision of the TRM (Am64x / AM243x Technical REference Manual (Rev. I.) from January 2026). Therefore I don't know the adress behind CTRLMMR_ADC0_CTRL and cannot change it with a HW_WR_FIELD32. Can you help me further on this point. Based on my research and your response regarding the configuration of a HW-based trigger the necessary steps are:

    - In line 177 (adcConfig.mode) use ADC_STEPCONFIG_MODE_HW_SYNC_ONESHOT from hw_adc.h 

    - Insert e.g in line 192 a single HW_WR_FIELD32(regAddr, REG_FIELD, fieldVal) with regAddr = CTRLMMR_ADC0_CTRL , REG_FIELD = bitmask for the desired event e.g 0x0000'0002 in case of EPWM SOCA_OUT, fieldVal = 1 if it should be enabled.

    Best regards,

    chr

  • 0 in reply to Christian Dev
    TI__Mastermind 21535 points
    Christian Dev said:
    I cannot find Table 5-192 in the current revision of the TRM (Am64x / AM243x Technical REference Manual (Rev. I.) from January 2026).

    Please check 14.2.1.1.1.2.115 MAIN_CTRL_MMR_CFG0_ADC0_CTRL in TRM (REV. I.)

  • 0 in reply to Meet Thakar
    Prodigy 30 points

    Hello Meet,

    thank your for your reply. The section 14.2.1.1.2.115 was what I was looking for. Just because I am curious: As an employee at TI, do you have a more detailed TRM, since as in your first answer you have section 5.1.1.5.72 with a table 5-192, which is missing in the current revision (Rev. I.)

    If anyone is trying to implement HW-enabled triggers for ADC, i summarized the necessary steps:

    1. The element 'mode' from the struct adcStepConfig_t must be set to e.g. ADC_STEPCONFIG_MODE_HW_SYNC_ONESHOT (from hw_adc.h)

    2. The bit 8 from register ADC_Control (Offset = 40h) must be set to 1

    3. The bits 4-0 from register MAIN_CTRL_MMR_CFG0_ADC0_CTRL (Offset = 4710h) must be set to the desired HW trigger source e.g. if you want to use TIMER0 set bit 3 to 1. For this step you can use HW_WR_FIELD32(regAddr, REG_FIELD, fieldVal). Have a look inside hw_adc.h how the _SHIFT and _MASK #-defines are implemented for other registers and add the ones you need. 

    4. By default, the MAIN_CTRL_MMR.... registers are write-protected. To unlock, LOCK1_KICK0 and LOCK1_KICK1 must be set to a specific Key (0x68EF3490U and 0xD172BC5AU). Only after this step it is possible to write the MAIN_CTRL_MMR_CFG0_ADC0_CTRL register. After setting the desired HW trigger make it write-protected again by writing '0x00000000' to LOCK1_KICK0 and LOCK1_KICK1'.

    Best regards,

    chr

  • +1 in reply to Christian Dev
    TI__Mastermind 21535 points

    Hi Christian,

    Thanks for summarizing all the steps here.

    Christian Dev said:
    Just because I am curious: As an employee at TI, do you have a more detailed TRM, since as in your first answer you have section 5.1.1.5.72 with a table 5-192, which is missing in the current revision (Rev. I.)

    I realized I was referring to an older TRM version, so I referred to Rev. I. to give you the updated section.