Part Number: AM263P4
Other Parts Discussed in Thread: DP83869
Hi,
The EtherCAT architecture snippet I’m referring to is from the following TI resource:
I am currently evaluating EtherCAT using PRU‑ICSS on the TI AM263P4 microcontroller and have a few questions regarding the implementation of the blocks shown in the diagram.
Layer 1 – Physical
My understanding is that this is implemented by the external Ethernet PHY devices (e.g. DP83869). Please confirm if this is correct.
Layer 2 – Data Link
The snippet suggests that the following components are provided by TI. Could you please confirm this and provide links or guidance on where to download them from?
-
PRUICSS with 2× MII
-
PRU Firmware
-
PRUICSS driver
-
FW HAL for EtherCAT slave
- EtherCAT Slave Stack - I understand this must be obtained from ETG upon membership, which is fine.
Layer 7 – Application
I understand this is user‑defined application code running on the Arm core.
Could you please confirm my understanding above and point me to the relevant documentation, example projects, or SDK components for AM263P4 EtherCAT slave implementation?
Also, the snippet below indicates that only certain AM263P4 device options include features such as the EtherCAT Hardware Accelerator, Pre‑integrated Stacks Enabled, and Pre‑integrated Stacks. Could you clarify what each of these feature categories specifically refers to?
In addition, are these feature options (E, F, L, M and N) available across all AM263P4 package variants (ZCZ‑C, ZCZ‑S and ZCZ‑F), or are they restricted to particular combinations?
Thanks for your support.
