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AM263P4: AM263P4 ECC in RBL

Pouya Sabouriazad
Prodigy 140 points

Part Number: AM263P4
Other Parts Discussed in Thread: AM2634

Hi,

I Have some questions regarding TCM and OCSRAM ECC. 

OCSRAM

It seems like the ECC for OCSRAM is enabled by default according to the AM263P4 Register Addendum where ECC Enable, Check and RMW fields have a value of 1 as their reset value. Is this correct? The reason I am confused is because in the following https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1448339/am2634-ecc-on-ocram-ocram-enabled-by-default, It is mentioned that the OCSRAM ECC is not enabled by default for AM2634 which has the same ECC Aggregator register definition as AM263P4.
RBL Initializes OCSRAM banks 0 and 1 completely. Since ECC OCSRAM is enabled by default, all the Error Correcting Code for bank 0 and bank 1 will be set correctly.  What would be the action of RBL when detecting 2-bit OCSRAM ECC error? Does it still pass control to SBL?

TCM

Unlike, OCSRAM, the TCM ECC should be enabled by software. Does RBL code enable the ECC on ATCM and BTCM? 
If the answer is no, what if a 1/2-bit error happens on TCM area that RBL uses? wouldn't that be a safety issue since during RBL execution we can be prone to SEU?

If the answer is yes, What would be the action of RBL when detecting 2-bit TCM ECC error? Does it still pass control to SBL?

Generic

The SDK ECC Code example uses a property for each RAM named "Stride", Does it represents the number of bytes that is used to generate a single Error Correcting Code? 

Thanks,

Pouya

  • 0
    TI__Guru* 75096 points

    Hi Pouya,

    Apologies for the delayed response!

    Pouya Sabouriazad said:
    It seems like the ECC for OCSRAM is enabled by default according to the AM263P4 Register Addendum where ECC Enable, Check and RMW fields have a value of 1 as their reset value. Is this correct?

    You are correct ECC enable and check bits are enabled by default for this device.

    Pouya Sabouriazad said:
    What would be the action of RBL when detecting 2-bit OCSRAM ECC error? Does it still pass control to SBL

    Actually, RBL will not perform any validations related to ECC. But it will do PBIST verifications for L2RAM, TCMA and TCMB. If any actual memory errors in these memories the corresponding PBIST verification will get fail right, if this happens then it will not call the SBL. And then RBL will just stuck in infinite loop without feeding watchdog, so after certain timeout this watchdog will reset the device and again RBL boot process will start again and this process continuous.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 140 points

    Hi Jagadish,

    Thank you for your response.

    So RBL won't check for any ECC errors on OCSRAM and won't enable the ECC on TCMA and TCMB. That means while RBL is running if a single bit or double bits flip due to SEU on the TCMA/TCMB memory location used by RBL, or if a double bits flip in OCSRAM memory location used by RBL, then RBL will end up consuming the flipped bits. wouldn't that be a safety issue since the code is using corrupt data? I do not think PBIST can detect an unintended bit flips due to an SEU.

    Thanks,

    Pouya