MSPM0G3507: Data Barrier Instructions & self-testing of pre-fetch and cache

Márton Ledneczki

Part Number: MSPM0G3507

Dear TI Forum,

I was wondering, are the ARM Cortex-M0+ ARMv6-M DSB, DMB, ISB instructions also used to empty, invalidate the prefetch buffer and/or the instruction cache?
Can the ISB instruction be self-tested?
Are pre-fetch and the I-cache standard ARM Cortex-M0+ components or something provided by Texas Instruments as an addition?
Is it possible to self-test somehow whether the pre-fetch and the instruction cache are working properly?

Thank you in advance for your help!

0 Diego Abad Sajamin 4 months ago

Hi Marton,
1. You can find the ways the dsb, dmb, and isb instructions are implemented inside the MSPM0 SDK

2. This seems to be an ARM related question outside the MSPM0 specifically. I will recommend to try and reach out the forums in ARM

3. We use the standard ARM Cortex-M0+ components. For more information in the MSPM0 CPU, check the CPU section in the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual (Rev. C)

4. There might be a way, though we don't provide examples for it.

Best Regards,

Diego Abad

Arm-based microcontrollers forum