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AM625: Feasibility of using LBCLKO pin (G25) for an alternate function (UART5_RTSN) during Standard SPI BOOT

iris kang
Prodigy 50 points

Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG

Hello TI Support Team,

I am currently developing a custom board using the AM6252ATGGHAALWR (AM62x Sitara Processor).

Our system is configured to boot from Standard SPI (MCSPI) — not QSPI or OSPI.
On our design, we have assigned the UART5_RTSN function to pin G25, which is the LBCLKO pin in the AM62x ALW package.

Before fabricating the PCB, we verified this pin-multiplexing configuration using the TI SysConfig tool and also went through a TI schematic review. No warnings were raised regarding the simultaneous use of Standard SPI boot and assigning UART5_RTSN to G25. Based on this, we proceeded with manufacturing our first bring-up boards, and they are currently booting without any issues at room temperature.

However, while preparing for our next board revision, I found a critical warning in TRM Section 5.4.1, which states that for Low-speed SPI boot, the LBCLKO signal must be left unconnected (“absolutely no trace can be connected to LBCLKO”).

This is causing us some concern. If using G25 is strictly prohibited in Standard SPI boot mode, we would be forced to reassign UART RTS to UART0, which is currently dedicated to our internal debug interface — resulting in a noticeable design impact.

Therefore, I would like to request your official guidance on the following points:

Is it absolutely forbidden to use pin G25 (LBCLKO), even if it is muxed to UART5_RTSN, when using Standard SPI Boot?

Does the presence of any physical connection or routing on this pin interfere with the internal loopback circuitry or compromise the Standard SPI boot process in any way?

Any clarification you can provide would be greatly appreciated.
Thank you very much for your time and support.

Best regards,

  • 0
    TI__Guru**** 227965 points

    Hello Iris Kang,

    Thank you for the query.

    Let me  review the inputs and also check with the team and update.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 227965 points

    Hello Iris Kang,

    Can you please confirm the TRM revision you are using.

    Below is the inputs i received from the expert:

    The customer must also consider the case when the ROM boot code loads a secondary boot loader that configures the OSPI peripheral to operate differently that the description provide in the TRM.  The customer must also understand which clocking topology is used by any secondary boot loader and application code before making a decision on using the OSPI0_LBCLKO for any other signal function.

     Here is the fundamental requirement:

     They must not connect any signal trace to the OSPI0_LBCLKO pin if the OSPI peripheral is ever configured to use the “Internal Pad Loopback” clocking topology.

    Can you confirm if the memory device is used after boot and the configuration used.

    Regards,

    Sreenivasa