Part Number: AM2612
Hello!
I'm currently trying to integrate a IS66WV032 PSRAM with the OSP1 peripheral on a custom hardware witha TI AM2612 chip.
The main issue is the Phy Mode and DQS Signal to correctly sample the input data. As long as the PHY mode is not enabled I'll get the necessary CLK cycles for address, and dummy until the data is sampled. As far as I understood, will the OSP1 peripheral sample the data at the SCLK cycles if the PHY mode is disabled. Only with the PHY mode enabled, the DQS signal is used to sample the data.
If I enable the PHY mode I'll only get one SCLK cycle which is of course not enough to trigger address, and the necessary dummy cycles until the DQS signal is given.
What am I missing to correctly configure the PHY Mode?
The relevant phy configuration (omitting configuration of address and dummy cycles which seems to work with disabled phys):
/* Select the number of delay element to be inserted between
* phase detect flip-flops.
*/
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_MASTER_CONTROL_REG,
OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,
2U);
/* Configure PHY in Master operational mode */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_MASTER_CONTROL_REG,
OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_MASTER_BYPASS_MODE_FLD,
OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_MASTER_MODE);
/* Set the read delay */
CSL_REG32_FINS(&ospi1_flash_cfg->RD_DATA_CAPTURE_REG,
OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG_DELAY_FLD,
5);
/* Sampled on rising edge of clock */
CSL_REG32_FINS(&ospi1_flash_cfg->RD_DATA_CAPTURE_REG,
OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG_SAMPLE_EDGE_SEL_FLD,
CSL_OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG_SAMPLE_EDGE_SEL_FLD_MAX);
/* Try RX DLL BYPASS ?? */
// CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG, OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_RX_DLL_BYPASS_FLD, 1);
/* Set TX DLL delay */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG,
OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_TX_DLL_DELAY_FLD,
6);
/* Set RX DLL delay */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG,
OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_RX_DLL_DELAY_FLD,
6);
/* phy enable */
CSL_REG32_FINS(&ospi1_flash_cfg->CONFIG_REG, OSPI_FLASH_CFG_CONFIG_REG_PHY_MODE_ENABLE_FLD, TRUE);
uint32_t idleFlag = 0;
/* Wait for Idle */
while (idleFlag == 0)
{
idleFlag = CSL_REG32_FEXT(&ospi1_flash_cfg->CONFIG_REG,
OSPI_FLASH_CFG_CONFIG_REG_IDLE_FLD);
}
/* Disable OSPI Controller */
CSL_REG32_FINS(&ospi1_flash_cfg->CONFIG_REG,
OSPI_FLASH_CFG_CONFIG_REG_ENB_SPI_FLD,
FALSE);
/* Clear the delay line resync bit */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG,
OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_RESYNC_FLD,
0U);
/* Reset DLL in master mode */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG,
OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_RESET_FLD,
0U);
/* Set Initial delay for the master DLL */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_MASTER_CONTROL_REG,
OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_MASTER_INITIAL_DELAY_FLD,
0x5U);
/* DLL out of reset */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG,
OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_RESET_FLD,
1U);
/* Wait DLL lock done */
while ((CSL_REG32_FEXT(&ospi1_flash_cfg->DLL_OBSERVABLE_LOWER_REG,
OSPI_FLASH_CFG_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD) == 0U))
{
(void)idleFlag;
}
/* Wait DLL loopback lock done */
while ((CSL_REG32_FEXT(&ospi1_flash_cfg->DLL_OBSERVABLE_LOWER_REG,
OSPI_FLASH_CFG_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD) == 0U))
{
(void)idleFlag;
}
/* Resync the Slave DLLs */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG,
OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_RESYNC_FLD,
1U);
/* enable SPI */
CSL_REG32_FINS(&ospi1_flash_cfg->CONFIG_REG,
OSPI_FLASH_CFG_CONFIG_REG_ENB_SPI_FLD,
1);
