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MSPM0G3507: Clock synchronization issues

Dag.FF2
Intellectual 320 points

Part Number: MSPM0G3507
Other Parts Discussed in Thread: ADS131M08EVM, , ADS131M08, , TIDA-010243

Hello,

I'm attempting to fetch data samples from all 8 ADC channels on board the ADS131M08EVM, using the
LP-MSPM0G3507 and the Code Composer Studio [CCS] "Emeter_three_phase_TIDA010243_SW"
application example.  The current wiring between boards is:

      LP-MSPM0G3507                                               ADS131M08EVM
       (Controller)                                               (Peripheral)
 +----------------------+                               +-----------------------------+
 |                      |                               |                             |
 |                 J1:1 +--(3V3)--------------(GRN)-----+ DVDD (TP1)                  |
 |                      |                               |                             |
 |                J3:21 +--(5V)---------------(RED)-----+ R70PAD (EVM_RAW_5V)         |
 |                      |                               |                             |
 |     J2:18 (PB17)[14] +--(!DRDY)--------<---(BLU)-----+ [18] J10:6 (!DRDY)          |
 |                      |                               |                             |
 |     J3:25 (PB18)[15] +--(SYNC/RESET)--->---(BRN)-----+ [16] J10:1 (SYNC/RESET)     |
 |                      |                               |                             |
 |     J3:24 (PA22)[18] +--(M0_CLKOUT)---->---(ORG)-----+ [23] JP10:2 (8.192 MHz)     |
 |                      |                               |                             |
 |      J2:13 (PB6)[58] +--(!CS0)--------->---(YEL)-----+ [17] J10:4 (!CS)            |
 |                      |                               |                             |
 |      J2:14 (PB7)[59] +--(POCI)---------<---(VIO)-----+ [20] J10:7 (DOUT)           |
 |                      |                               |                             |
 |      J2:15 (PB8)[60] +--(PICO)--------->---(RED)-----+ [21] J10:2 (DIN)            |
 |                      |                               |                             |
 |       J1:7 (PB9)[61] +--(SCLK)--------->---(GRN)-----+ [19] J10:5 (SCLK) 8.192 MHz |
 |                      |                               |                             |
 |           J2:20 [41] +--(GND)--------------(BLK)-----+ [13|25|28] J10:8(GND)       |
 |                      |                               |                             |
 +----------------------+                               +-----------------------------+

What works so far:

SYNC/RESET: ~300ms
      !CS0: Active Low for ~30-byte data frame
      POCI: Fixed to 30-byte data frame [DOES NOT RETURN expected 0x050000 SYSTEM STATUS]
      PICO: Fixed to 30-byte data frame [UNLOCK:Ox065500 + CHKSUM]
      SCLK: On for 30-byte frame bursts @ ~8.192 MHz 

Issues:

1. Unable to obtain a Master Clock (M0_CLKOUT) output, configured for 8.192 MHz, between
the LP-MSPM0G3507 and the ADS131M08EVM.  The CLK_OUT was configured for an 8.192 MHz [HFCLK/2]: the output detected at LP-MSPM0G3507 [J3:24] is ~20.16MHz.

2. Code excecution, specifically at the ADS131M08_init() function call, exits prematurely
at the clock test:


if(!ADS_writeSingleSPIReg(adsHandle, CLOCK_ADDRESS, ADS131M08_CLOCK_ADDRESS_DATA, TRUE))
{return false;}

Questions:

1. Is the wiring between boards, illustrated above, adequate to fetch ADC data from the ADS131M08EVM?


2. Do both CLK_OUT and SCLK need to be synchronized?  If so, what are the best practice
recommendations for synchronization between the LP-MSPM0G3507 and the ADS131M08EVM?


3. Using the syscfg tool in CCS, what specific steps should I follow to obtain the desired
8.192 MHz output at the LP-MSPM0G3507 [CLK_OUT] (J3:24)?


4. Does CLK_OUT need to be configured for output on a different MSPM0G3507 pin?

Please advise.  Thanks for your help.

Best,

Dag.FF2

  • 0
    Guru 102645 points

    According to the Launchpad User Guide (SLAU873D), the HFCLK crystal (Y2) is 40MHz, so HFCLK/2 would be 20MHz. The EXCLKDIVVAL-s are all even, so you could get 40/4=10MHz or 40/6=

    [Edit: Truncated --  "An error occurred."]

  • 0 in reply to Bruce McKenney
    Guru 102645 points

    6.667MHz. The latter is at least within the range (0.3-8.4MHz) in ADC datasheet (SBAS950B) Sec 6.3.

    It looks like PA22 can be used as an output from a few different timers [Ref datasheet (SLASEX6C) Table 6-2]. Generating the ADC clock with a timer would allow you a divisor of 5 (LOAD value of 4) to get 8.0MHz.

    I don't know if it's a requirement to sync SCLK with the ADC CLKIN but it's probably a good idea. If you (also) run MCLK/ULPCLK from HFCLK, this will happen implicitly.

    [Edit: Several false-starts since "An error occurred."]

  • 0
    TI__Mastermind 31185 points

    Hi Dag,

    You can check the schematic of the TIDA-010243 for the hardware setting: https://www.ti.com/lit/df/tidmbp3/tidmbp3.pdf 

    The data transmission looks good.

    Dag.FF2 said:
    2. Do both CLK_OUT and SCLK need to be synchronized?  If so, what are the best practice

    I believe the sync of these two clock is not hard required, as the SCLK is used to generate clock for SPI transmission. You can double check with ADS team.

    Dag.FF2 said:
    3. Using the syscfg tool in CCS, what specific steps should I follow to obtain the desired
    8.192 MHz output at the LP-MSPM0G3507 [CLK_OUT] (J3:24)?

    Bruce is correct, the project does not work for LP-MSPM0G3507 with default HFXT which is 40MHz. It is used for the TIDA-010243 board.

    Dag.FF2 said:
    4. Does CLK_OUT need to be configured for output on a different MSPM0G3507 pin?

    This does not help, as the LP-MSPM0G3507 can not generate the 8.192 MHz clock. You can replace a HFXT in the LP to test. Or you can test the TIDA-010243 board with the code example.

    B.R.

    Sal